PGA2320 not accepting volume changes when audio signal not present

Hello FG,

Using the PGA2320 bench test board, I performed a few experiments.  So far,  I have not been able to reproduce an issue where the PGA2320 takes longer than the timeout period of 16ms to change the volume when ZCEN is enabled.

I have set up the device with ZCEN pulled high and set up the device with no signal source, zero signal and a signal; and monitor SDO of the device to determine if the data is being shifted.  The gain byte seems to change as expected. I also tried a few experiments powering up and powering down; with signal and without signal; and the gain seems to change accordingly.

How have you determined that the volume is not changing when the source signal is muted?  Is it possible that this is a communication/software issue?

How much time is allowed for the supplies and the device to turn on after the power /down/up cycle and when the new gain settings are sent? If an schematic is available, we could review it.

Thank you and Best Regards,

Luis

Hi Luis

Thank you very much for your reply.

I discovered this issue when first performing simple auditioning tests on the newly completed device. I initially thought that everything was working fine, since I was power cycling it with a signal source connected. It was when I powered it up with the source  (an MP3 player) turned off, that I discovered that when the MP3 player was turned on nothing could be heard on one or both channels. If one channel was missing it was always the left channel (although this is arbitrarily assigned and might appear as the right channel in a different implementation). In either case it was necessary to send a volume change command to the device 2 or 3 times before both channels would suddenly apparently accept the command and settle down with both channels at the commanded level. Up/down control is by momentary push-button and individual left/right control is possible, but of course both channels are written when either or both are changed.

My presumption is that there is no problem with the software or power-up sequencing since everything works fine with the signal present, and once the system has settled down there appears to be no problem, even, as I have since determined, if changes are made with the source turned off. It's fair to say that there is no power sequencing as such, all the ICs in the system are simply connected to a switch (relay) and power is applied simultaneously to all. There are numerous 47u tantalum capacitors and 0u1 ceramic (0805) caps distributed on the 2 boards.

I have built up a second prototype which behaves identically to the first.

The uproc (PIC16F887) performs a number of housekeeping (setup) tasks, retrieves the stored settings from flash and sends them to the PGA chip. There is some delay, as the uproc writes a moving welcome ('HI') to the 3 multiplexed 7-segment displays before writing to the PGA. This takes a few seconds (a lifetime in electronic terms), so I thought the PGA chip should have fully initialised by then. The values are sent using the technique called bit-banging. No internal UART or other serial device in the uproc is employed, 3 pins are simply assigned as SCK, SDI and $CS$. The bytes to be written are reprocessed by an internal routine into a memory array, interrupts are disabled, and the array bytes written to the port containing the 3 output pins, the effect being that the first data bit is set up on SDI, $CS$ is set active, and SCK is toggled. As the array is written successive data bits are clocked into the volume control and $CS$ is eventually disabled, when interrupts are re-enabled.

In desperation I inserted a routine which writes out the volume setting, waits for a short period and repeats 10x. This has resolved the problem, and I do not see the additional delay on power up as being a problem. Now the device starts up working at the stored volume setting. There appears to be no problem with subsequent changes to the setting regardless of whether there is a signal present or not. I was initially writing out the value 3 times without resolving the problem. It could be that I can decrease the number of writes without the problem reappearing, but there is no urgency to discover this on my part.

A schematic and copy of the uproc C code are available if you wish to pursue the matter further, but the heat has gone out of the issue as far as I am concerned and I have other concerns with trying to put the product into production.

Thank you for your time. Please ask if you wish to see the schematic and code, but bear in mind that it is commercially sensitive information that I don't want to put in the public domain just yet.

FG

Hello FG,

Thank you for letting me know the details. I have not been able to reproduce the issue as far, but I plan to perform a few more experiments using the bench set up to see if I can reproduce this behaviour.  What voltage (VA and VD) is being used on your application?  If you wish to send me an schematic/code, my email is l-chioye@ti.com. 

Thank you again,

Best Regards,

Luis