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problem TAS5630 in PBDT mode

Other Parts Discussed in Thread: TAS5630

Hi,

I use TAS5630 in my design of D power amp (300W) with a transformer load in PBTL mode. I followed all recommendations of  PCB, sloa133.pdf, heat sink have a good connection to PCB ground. But I found a problem, TAS5630 damaged after different times of work (sometimes 5-10 sec. sometimes 1-2 min). I know about different protect systems in TAS5630. That’s why I tried to know the situation and changed the load (resistance load) so that I had the power 300W. In that schema I found out the strange effect, PWM frame rate in OUT_X (400kHz I have in my design) changed according figure.

It’s like a change of PWM frame or a miss of a pulse that must be at list 250ns according page 10 tas5630.pdf. I changed the resistance load (4-Ω, 3-Ω, 2-Ω) and I found out that the missing of pulses took place when the amp power was about 220-240W in any load (4-Ω, 3-Ω, 2-Ω or else) and when the input sine went over its max and min. At the same time I had clip signal when the amp power was about 150W but according tas 5630.pdf that situation didn’t happen till RL = 2 Ω, 1% THD+N, unclipped output signal -480W page 10. According some recommendations of DC-DC converters I divided power GND and signal GND in my PCB design but without any result. I cant explain such a behaviour and ask your help.

Thanks and regards

Sergey Chernov.

  • Hi Sergey,

    Can you please describein detail how the device is damaged after a few seconds of operatino? I would like to know the operating conditions such as PVDD, Load, Po. Does your design follow the EVM exactly? If not what are the differences. Can you share your sch and layout?

    reg,

    Paul.

    Applications Engineer

    Dallas TX USA

  • Hi Paul,

    As I discribed my D power amp TAS5630 has a transformer load in PBTL mode. An active load on the transformer's out is 58Om. Transformer is 1:4, that's why I have about 30V on the transformer's in and 120V on out (It's about 300W). PVDD=48-52V from accumulator. In first time I change reset signal to high level, after 150 us I have input signal f=1000Hz. In that moment I see the situation TI described in sloa133.pdf (SD signal go low level for several cyrcles but after that go high level and I have normal signal to the active load). I found it normal, but after several times (50-100) of turning off and on according the same algorithm SD signal went low and never changed. I analysed the problem and found out that one of OUT_A or OUT_B or OUT_C or OUT_D was damaged (had 0Om between GND and OUT_X). I repeated that experiment about 15-20 times, I divided power GND and signal GND in my PCB design, did heat sink's good connection to PCB ground, chaneged PWM period and different more, but had the same. My sch, layaut is in files and componens are according TAS5630DKD2 Evaluation Module.6114.PCB.pdf5722.Sch.pdf

    Sergey,

    Head engineer radio disign bureau

    Vladimir, Russia

  • Hello Sergey,

    Thanks for posting the information. I will review this and get back to you.

    reg,

    Paul

    Applications Engineer

    Dallas TX USA.

  • Hi Sergey,

    Based on your description, it seems the over current protection of TAS5630 is tripped possibly due to the in-rush current of the transformer.  I would recommend monitor the voltage waveforms at the outputs, PVDD and BST pins to see if there is any voltage spike that exceeds the abs max rating of the device.

    http://www.ti.com/lit/an/sloa133/sloa133.pdf

    http://www.ti.com.cn/cn/lit/an/slea025a/slea025a.pdf

    reg,

    Paul.