TAS5706 Audio data verification

Hi, Paul,

Welcome to e2e, and thanks for your interest in our products!

The TAS5706B requires MCLK, SCLK, LRCLK, and of course, SDINx, in order to play audio. Use an oscilloscope to make sure these signals are all present. NOTE: our device requires ALL four signals be applied to the IC for it to play audio. The data sheet is a little confusing in this area. If you don't have MCLK, SCLK can be applied to the MCLK pin for certain fs ratios.

The start-up sequence is described on page 39 of the data sheet.

The device is a slave-only device as discussed on page 1 of the data sheet.

You can find the data sheet at: http://www.ti.com/lit/ds/symlink/tas5706b.pdf

-d2

HI,

D2

TAS5706 will work if PDN is remain as a float? Or its better to give alway VCC?

It is possible to give data on SDIN1, and put other ping SDIN2 float?

-Paul

Hi, Paul,

According to page 7 of the TAS5706B data sheet, PDN has an internal pull-up, so yes, it is ok to leave it floating.

Yes, if you only have one I2S source, you can leave SDIN2 floating.

Please double-check your I2C commands. It's always a software problem. :)

-d2

Hi,

Thanks for confirming this.

Can you please provide minimum I2C setting command for 48Khz stereo playback?

What will be the MCLK and other clock value?

For Chip initialization do i need to follow the steps after playback starts? ( Page 39- Setups 3,4)

Can you please explain this sequence?

-Paul

Hi Paul,

The following I2C commands should get the audio streaming....

0x1B   - x00 (Trim)

0x05   - x00 (Exit Shut-Down)

0x07   - x?? (Volume) e.g. for 0dB setting, use x30

The valid clock inputs are described in the description of register 0x00. For LRCK=48KHz, you can use MCLK=SCLK=64*Fs.  

-Ravi

HI,

From the data sheet MCLK value should be in the reange of 4.9 MHz to 49MHz.

If you say MCLK = 64* Fs  , Here Fs == 48KHz ?

then MCLK = 3MHz. will it work?

-Paul

Hi,

During song playback i have done chip reset and follwoed the TAS5706 chip initialization steps.

I got PLL auto lock error. (PLL autolock error --> ERROR STATUS REGISTER (0x02)).

How to fix?

-Paul

Paul,

This is likely an issue due to invalid I2S clocks. Have you verified the I2C clock rate's  provided to the device are valid ? (Register 0x00 in data-sheet shows for valid clock-rates).

-Ravi

Paul,

I just re-read your post. It sounds like you were able to play audio (so the clock-rates must be valid). 

After asserting RESET and re-initializing the I2C registers, does the audio continue to play? Note that the error-register read-back is "sticky" i.e. it needs to be cleared by writing x00 before read-back. -- Does the register read-back continue to indicate clock-error after being cleared?

-Ravi

Hi,

I am getting contiue error.

Follwoing are the I2C commands.

 I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_OSCILLATOR_TRIM_REG, 0);    

 //Wait 50 ms while the part acquires lock.    

 msleep(50);    

 //Exit all-channel shutdown (write 0 to bit 6 of register 0x05).    

 I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SYSTEM_CONTROL_2_REG,0x40);    

 I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SYSTEM_CONTROL_2_REG,0x60);    

 I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SYSTEM_CONTROL_2_REG,0x0   );        

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_MASTER_VOLUME_REG,0x30);

 I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SERIAL_DATA_INTERFACE_REG, 0x3); //I2S (32 fS SCLK)    

 I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_CLOCK_CONTROL_REG, 0x75); //48 KHz and 512 * fs  

I am playing 48KHz stereo file.

LRCLK -> 48000  (fs)

SCLK --> 3072000 (64 * fs)

MCLK -> 24576000 ( 512 * fs)

Do i need to change anything?

- Paul

Hi

Any sugettions?

-Paul

Any comment for Above control register setting for 48Khz playback?

Hi Paul,

Are you running the tests on the EVM or a different board?

-Ravi

Hi,

Ravi

We are using different hardware.

form my processor all the clock are coming.

But I am getting error in clock control register.

I have done chip reset after playback has started so Codec gets stable clock.

Also check above I2C commands and clock vales so it will be helpful.

-Paul

Hi, Paul,

Ravi is out for a few days, so let me jump in here.

Looking thru the thread, it's not clear if you understood what Ravi meant by the clock error bit is "sticky."

This means if there is ever a clock error, the bit will be set, and later, the clock issue is fixed, the bit will still be set. Basically, what we do is write 0x00 to it, and then read it. If you have a real clock error, this insures you will get the correct status.

-d2

Hi,

D2

Can you answer the follwoing query?

"

Hi,

I am getting contiue error.

Follwoing are the I2C commands.

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_OSCILLATOR_TRIM_REG, 0);   

//Wait 50 ms while the part acquires lock.   

msleep(50);   

//Exit all-channel shutdown (write 0 to bit 6 of register 0x05).   

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SYSTEM_CONTROL_2_REG,0x40);   

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SYSTEM_CONTROL_2_REG,0x60);   

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SYSTEM_CONTROL_2_REG,0x0   );        

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_MASTER_VOLUME_REG,0x30);

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_SERIAL_DATA_INTERFACE_REG, 0x3); //I2S (32 fS SCLK)   

I2C_WriteByte(objtas5706_priv.client->addr, TAS5706_CLOCK_CONTROL_REG, 0x75); //48 KHz and 512 * fs 

I am playing 48KHz stereo file.

LRCLK -> 48000  (fs)

SCLK --> 3072000 (64 * fs)

MCLK -> 24576000 ( 512 * fs)

Do i need to change anything?

"

Hi Paul, Saurabh,

Here are the write's that should get audio playing

x1B  x00 (Trim)

x05  x00 (Exit-Shutdown)

x07  x30 (Unmute & set volume=0dB).

If the clock's are valid and are within the rise/fall time spec's, there should be no issues.

Note that the register 0x00 is read-back only (in clock auto-detect mode).

If you continue to have issues, I would recommend running a debug check with the clocks from the EVM controller-board routed to the the target application board.

-Ravi

To follow-up on the previous comment, the other thing to ensure (other than valid clock's) is the external components used on the diital pin's (e.g. PLL) are of the correct values & in the right configuration. Please refer to the EVM schematic for reference.

-Ravi