Frame slip error on TAS5706B

Saurabh Patel

Other Parts Discussed in Thread: TAS5706B, TAS5706

Hi,

Can you explain about Frame slip error ERROR STATUS REGISTER (0x02)?

How to fixe this issue?

MCLK = 64 * fs is valid for 48000 sampling frequency? If it is true then what about MCLK limit mentioned in TAS5706B data sheet?

Data sheet page number 7

"MCLK is the clock master input. The input frequency of this clock can range from 4.9 MHz to 49 MHz"

Saurabh.

over 11 years ago

0 Don Dapkus over 11 years ago

TI__Guru**** 189399 points

Hi, Saurabh,

I have asked my colleague to look at your post.

-d2

0 Jacky Wang(QD) over 11 years ago

TI__Genius 10390 points

Hi Saurabh,

Frame Slip Error means that LRCLK phase is drifting with respect to internal frame sync. Do you use the clocks we recommended?

TAS5706 can works for MCLK=64xFs, Fs=44.1kHz/48kHz, but we don't recommend to use by this for reliability consideration. For the available MCLK, please refer to below table:

Thanks.

0 Saurabh Patel over 11 years ago in reply to Jacky Wang(QD)

Intellectual 590 points

Hi,

I have set follwoing clock settings for 48KHz stereo file.

With this settings i am getting PLL audo lock error.

MCLK --> 512 * fs --> 24576000

SCLK --> 64 * fs

MCLK --> 48000

0x1B 0x00 (Trim Register)

0x00 0x75

0x05 0x00 (Exit Shut-Down)

0x07 0x30 (Unmute & set volume). 0x30 will set a 0dB master volume.

--> What is a value do i need to set for Bit clock (SCLK) frequency = 64 × fs in (Serial Data Interface Control Register).

0 Jacky Wang(QD) over 11 years ago in reply to Saurabh Patel

TI__Genius 10390 points

Hi Saurabh,

I have tested it on our EVM board using AP PSIA output,

MCLK=512xFs=24.576MHz

BCLK=64xFs=3.072MHz

LRCLK=48kHz

0x1B 0x00 (Trim Register)

0x00 0x78 // f_S= 48-kHz sample rate, MCLK frequency = 512 × f_S,Bit clock (SCLK) frequency = 64 × f_S

0x05 0x00 (Exit Shut-Down)

0x07 0x30 (Unmute & set volume). 0x30 will set a 0dB master volume.

0x04 0x05 // I2S

It works fine without any errors, can you try above setting again?

BTW: What you used to provide these clocks to TAS5706B? Are these clocks good enough without any deviations and jitters? You can also check the rising/falling edge for your clocks are matched with our spec.

Thanks.

0 Don Dapkus over 11 years ago in reply to Jacky Wang(QD)

TI__Guru**** 189399 points

Hi Saurabh,

Do you have any audio output?

Keep in mind that register 0x02 is "sticky" and will often get an error at start-up as the clocks are coming up. You have to write 0 to it before reading it to see if you're actually experiencing a frame slip error at that exact moment in time (and not some time back in history...).

-d2

0 Saurabh Patel over 11 years ago in reply to Jacky Wang(QD)

Intellectual 590 points

Hi,

device ID register contains is = 0x2A (firmware number)

0 Jacky Wang(QD) over 11 years ago in reply to Saurabh Patel

TI__Genius 10390 points

Hi Saurabh,

The ID you read out is correct, and what's your progress for this now?

Thanks.

0 Saurabh Patel over 11 years ago in reply to Jacky Wang(QD)

Intellectual 590 points

Hi,

I found two different revision for TAS5706 datasheet.

Both has diffrenet explanation for clock control register. Which datasheet should i have to refer for 0x2A firmware number.

I am getting PLL auto lock error. Can you explain me detail infromation about it?

0 Saurabh Patel over 11 years ago in reply to Saurabh Patel

Intellectual 590 points

Hi,

Ravi

To get output working I need to change

- Use same clock source to generate Bit clcok, LRCLK, MCLK.

- Code change CLOCK CONTROL REGISTER (0x00) value according to updated datasheet.

I think old datasheet link should be removed from the site.

for new developer it will be easy.

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Frame slip error on TAS5706B