TPA5050/TPA5051 Behavior When It Does Not Supply Clocks

Hi Kato-san,

If the supplies of BCLK and LRCLK are cut off, the delay will not be active and the data-out will follow the data-in (no delay).

Regards,

~John

Hi John-san,

Thank you for your reply quickly.
If we modify default settings to other settings for audio delay registers by using I2C interface, supply the BCLK, LRCLK and Data,
we believe that the signal which delayed depending on register settings is output from the DATA_OUT terminal.
Then, if the supplies of BCLK and LRCLK are cut off, does the output mode become the rhrough mode automatically?
This means that audio delay registers becomes all zero data.
Is it correct?

Moreover, which clock do these deivces operate as the master clock?
We believe that the master clock is BCLK.
Could you please advise us?

Best Regards,
Kato

Hi John-san,

Thank you for your cooperation.
We understood your information, had one more question.
Because these devices have the delay memory, operate on the BCLK and LRCLK, do not have internal PLL.
Is it correct?

Best Regards,
Kato

Kato-san,

You are correct.

-d2

Hi, Don-san,

Thank you for your cooperation.
We understood it.
Thank you so much.

Best Regards,
Kato