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I2S FORMAT WITH pcm4104, pcm4204

Other Parts Discussed in Thread: PCM4204EVM, PCM4204, PCM4104, PCM1802, PCM1728

Attempting to connect C6713DSK to (2) PCM4204EVM’s ADC’s and (1) PCM4104EVM DACs. Eight channel of input, 8 channels of output.

Using McASP1 (I2S Format) as master to generate clocks and outputs to DACs, McASP0 is configured as slave with inputs from ADC’s.

LRCLK = 48kHz = Sample Frequency (Fs) = (actual measurement 48.8kHz)

BCLK = 3.072MHz = Fs * 64 (actual measurement  = 3.125MHz = 48.8kHz * 64)

HCLK = 12.288MHz = Fs * 256 = (estimated actual = 12492.8)

PCM4204 switch settings:

SW1

FS0   LO

FS1   LO

FS2   LO

S/M   HI

FMT0 HI

FMT1 LO

FMT2 LO

HPFD LO

SUB   LO

/DSDTEST HI

SW3

MONO34 LO

MONO12 LO

FMT1      LO

FMT0      LO

CLK0      LO

CLK1      LO

/DIT        LO

SW5

OSC1  LO

OSC2  LO

/EXT    HI

 

PCM4104 switch settings:

SW1

MODE = LO

MUTE = LO

DEM0 = HI

DEM1 = LO

FMT0 = HI

FMT1 = LO

FMT2 = LO

FS0 = LO

FS1 = LO

SW3

/ASP = LO

TDM = LO

I have previously connected the C6713DSK to a homemade board with PCM1802 ADC’s and PCM1728 DAC’s. Even with 24” long sloppily wired clocks and data lines, this works fine, just a little noise on the analog inputs that I want to eliminate by going to PCM4104s and PCM4204s. Plus the PCM1728 is out of production so I’ll have to change that regardless.

I can hear a little bit of the actual audio signal under the very loud noise that I believe is caused by poor quality clocking signals. I have shortened the clocks and data lines to 18” with little improvement.

From PCM4204 data sheet, page

For Left Justified, Right

Justified, and I2S data formats, the BCK rate is typically

128fS in Single Rate sampling mode, and 64fS in Dual or

Quad Rate sampling modes. Although other BCK clock

rates are possible, they are not recommended due to the

potential for clock phase sensitivity issues, which may

degrade the dynamic performance of the PCM4204.

If I understand this correctly, since Fs = 48kHz, I should use Single Rate sample mode, and the BCLK should be 128 * Fs. How does this work when (32-bit Word * 2 channels = 64 bit length). Are you saying that there would be 64 BCLKs for the 32 bit Left channel data, then 64 BCLKs for the 32 bit Right channel data.

I have also noticed that there is a newer “high reliability” version of the PCM4104. If I change the current chips on the PCM4104EVM’s to the “high reliability” version, will this improve my situation?

Any help would be greatly appreciated.

Thanks

Jim Andrew

  • Hello Jim,

    your estimates are correct. The data should be padded out to 64BCLKs per channel in the LRCLK. This should be taken care of in your DSP. (doesn't *usually* require more than a few McASP setup registers - however, being in our analog organization, I can't tell you exactly WHICH ones)

    The Hi_rel IC's are for Industrial/military applications. The behaviour of the serial port is not expected to change.

    Best Regards

    Dafydd Roche