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Other Parts Discussed in Thread: TPA3251, TPA3255, TPA3251EVM, TPA3255EVM

Does mode selection shown in Table 1 of TPA3251D2 ds affect operation other than the protection channel grouping shown in Table 3?

Information for 2.1 mode is missing on Table 3 as is diagram in applications section. Which channel pair should be BTL?

What is meaning of notation in column 3 of Table 1, "INPUT MODE"?

If used in SE mode with unbalanced signals is there an overvoltage shutdown in case of supply pumping?

Is muting inputs during startup necessary?

Is TPA3251D2EVM User's Guide, SLVUAG8 available?

  • Hi Greg,

    Thanks for choosing TPA3251D2 for your application. The mode selection in table 1 impacts the device mode of operation, which includes the channel protection in table 3. The 2.1 mode is covered in table 3, since it refers to one BTL channel and two SE channels. In 2.1 mode OUT A and B are BTL and OUT C and D are SE.

     There's no overvoltage protection in this device. Is your power supply source only or can it regulate voltage by sourcing and sinking current. Supply pumping in SE is mostly an issue for source only supplies. The PVDD bulk caps on the board should help minimize supply pumping as well. Please refer to this post on supply pumping in SE class D application:  

    Input mode 2N+1 is differential input and 1N + 1 is single-ended input configuration. In (2.1) 1 X BTL + 2 X SE, INA and INB are differential inputs and INC and IND are single-ended inputs.

    Muting is recommended since TPA3251D2 doesn't have a volume ramp during startup, so the audio will start up at the level of the input signal with ~20dB gain.

    The EVM user's guide will be released next month.

  • Dear Damian,

    your answer makes me wonder. Figure 28 in the TPA3251D2 datasheet states a "t_startup_ramp" for VOUTX. Doesn't the ramp time corresponds to the value of Cstart at pin 15?

    We just finished a first layout to see how good this new chip performs.

    Are there any additional thermal calculations for BTL performance? (My calculations leads into a heatsink with <=3K/W for full power rms performance)

    I also miss a plot for CMRR and PSRR. The now (down)corrected value of 60dB PSRR for BTL isn't that great, would guess it's getting (much) worse when using SE mode.

    Please have a look for our PCB design here:

    (Please excuse the automatic english translation)

    Kindly regards,

  • Hi Christian,

    PSRR is 60dB with Cstart=10nF in BTL mode. It can be increased to 80dB by increasing Cstart to 100nF. In SE mode, Cstart is 1uF, so PSRR is helped. No plots are available, but PSRR is quite flat with frequency up to at least 10KHz.

    EVM seems to have provision for post filter feedback any application info available?

  • Hi Gregory,

    We provided the capability for PFF on the EVM in case there's an application need that can be resolved by this feature. We haven't investigated PFF on TPA3251D2, since the audio performance is very stellar. Do you have an application need that TPA3251D2 can't meet the performance and is in need of PFF?

  • reduction of hf response variation with load impedance

  • Dear Damian,

    As the TPA3251 Datasheet lacks data on loop gain and phase margins, are there suggested starting points to test PFNFB? 

    The EVM suggests 10K feedback resistors from the output (which makes sense as the internal feedback combo seems around 24k/240k), what would be the minimum stable gain for PFNFB, or n other words, what would be a good starting point for the values of R4, R12, R44, R46?

    If using suitable compensation to retain stable noisegain, could the final gain be adjusted freely (e.g. below unity)?

    Kind regards Thorsten

  • Hi Thorsten,

    We are working on an application note for both TPA3251 and TPA3255. It should be ready by the end of July. Here is some points so you can get started. 


  • Dear Damian,

    Excellent, many thanks.

    Kind regards T

  • Hi,

    In my view there is a mistake in slaa702.pdf - "TPA3251 and TPA3255 Post-Filter Feedback (PFFB)".

    On page nuber 6 is written:

    "With the TPA3251EVM, the actual gain in PFFB was measured to be 11 dB. With the
    TPA3255EVM, the measured gain was 12.2 dB."


    "The reduction in gain is primarily due to losses in the output inductor and the non-zero output
    impedance of the input op-amp stage not accounted for in the feedback factor β"

    In my view reduction in gain is due to input resistance of TPA3251 (24k).

    For low frequency output imedance of the input op-amp is near 0.
    Losses in the output inductor is below 0,1dB (R_inductor and R_speaker divider).

    Below I show simulation.

    But I have open loop -10 instead 10.

    Piotr Szymkowiak