Have some questions regarding the TAS54x4 parts and documentation:
The 5414C datasheet mentions paralleling ch1&2 or ch3&4, but doesn't say anything about paralleling all channels.
The 5414B datasheet doesn't mention that certain channels can be paralleled with other channels, just to ensure identical I2C settings for paralleled channels.
1a) Regarding paralleling of outputs, is there a limit of paralleling *two* outputs, or can three or four also be paralleled?
1b) Is there a difference between the ability or limitations on paralleling channels between the 'B' and 'C' versions of the parts?
2) If outputs are paralleled, is there a way (under software control) to selectively 'activate' only a portion of the outputs, thereby increasing efficiency (by keeping switching losses down) for lower power levels and 'activating' additional outputs as power requirements rise - Note: the intended application will not be an 'audio' application, so 'clicks' & 'pops' may not be of much significance
3) On page 43 of the online datasheet ( slos795e.pdf ) there is a pinout arrangement that seems contrary to the 'normal' arrangement and sequencing of most IC's when viewed from the 'top' (plan view)... The datasheet plan view, showing 'Thermal Pad (Up)', has pin #1 in upper left corner, with pin #s increasing in a CLOCKWISE direction around the part. The next page shows a drawing of the exposed thermal pad of the part (that is on the top of the part) with pin #1 shown in the lower-left corner of the part and pin numbers increasing in a COUNTER-CLOCKWISE direction around the part - typical numbering sequence... Which diagram is correct?
It appears the TAS5414C offered in 44 pin and 64 pin packages, but not the 36 pin package that the TAS5414B is offered in.
Would prefer to use the 36 pin package or 44 pin package (PowerPAD plastic small outline)
4) What is different about the TAS54x4C parts VS the TAS54x4B parts?
5a) Will the TAS5414B be available for several years?
5b) How many years before LTB? (is this part still recommended for new designs?)
6) Other than the voltage differences for the 0.47uF capacitors used in the output filters, there are 0.47uF and 470nF shown in the same section of the schematic - why mix units for the same value capacitors?
7) On pages 13, 14 & 15 of the TAS5414C EVM User Guide ( SLOU359 - January 2013), there is a 3.3V regulator near the top of each page - the schematic symbol for the regulator has the input and outputs 'reversed' - The input power to the regulator is connected to the regulator pin marked 'OUT' and vise-versa.
On page 43 of the TAS5414C-Q1 online datasheet, the pin numbering sequence has pin #1 in the upper left, increasing to the right in the plan view to pin #22 in upper right, then 'jumping diagonally' down to lower left for pin #23, increasing to #44 in lower right. The next page shows the same part with the exposed thermal pad, where pin #1 is in the lower-left (plan view), increasing pin #s to #22 in lower right, then up to upper right for pin #23 and across the top to upper left for pin #44 - more conventional pin numbering sequence.
8) What numbering is correct?
Typo Bottom of page 17 of TAS5414C-Q1 online datasheet: "Invoking of weeter detection is via I 2C, with individual..."
Page 32 of the TAS5414B-Q1 online datasheet, Demodulation Filter Design, last sentence:
The rule is that the inductance should stay above 10% of the inductance value within the range of peak current seen at maximum output power in the system design.
9) Can this be translated as: ensure output filter inductance drops by no more than 10% of nominal value at peak current?
Would really like to move forward with a layout, but need to ensure pin numbering questions are cleared up 1st.
Thanks,
Chris
