Hi,
I have a PGA2320 followed by two SN74AHC594 , giving a 32 bit chain: SDI-PGA-SDO-> ser 1st 594 -> QH' -> ser 2nd 594->QH'
I control the chain with a MSP430 SPI (SIMO, SOMI, CLK) and bit bang the /CS pin to load the serial data into the PGA and the 594 output registers after 32 bits have been shifted out in 4x 8 bit by the SPI SIMO and SPICLK. The QH' output of the last 594 feeds back into the MSP430 SOMI pin.
The SPICLK generates a total of 32 clock cycles, clocking data out at the negative edge, that is clocked in the PGA and the 594's at the positive edge.
Serial data is clocked back in the MSP430 SOMI pin on the rising edge of the SPI CLK.
The first 2 bytes read back correctly but the last two bytes are delayed with 1 bit position, so 0X55 55 55 55 clocked in reads out thenext time
as 0X55 55 AA AA.
The PGA SDO output is delaying the data output 1 bit after 16 clock cycles, causing this one bit shift
I see also the delayed bit coming out of the PGA after 16 clock cycles.
Any idea what can cause this?
I did not have a 100K pull down resistor at the SDO, as indicated in the PGA2320 datasheet (page 10) and found out this pin floats when /CS=high but adding the resistor makes no difference. I would be surprised if it did since the first 16 bits shift out correctly.
The reset pin becomes active high +/-200mS after the powersupply is up.
I checked the minimum VinH (2V) of the PGA which is OK for a 3V3 GPIO from the MSP430.
Also setup and hold times are way within spec since I am driving with a 100KHz clock signal.
ANy idea what causes this bit delay after 16 clock cycles?