TPA3124D2: What are the hi and lo logic levels for MUTE and SDn inputs?

My application is running a TPA3124D2 from +12V for AVCC and PVCC.  I want to exercise both the MUTE and SDn inputs, and I'd like to use a 74HC14 running at +5V Vdd to drive them.

I'm a bit confused by the phrase in your data sheet "TTL logic levels with compliance to AVCC";  I have a pretty good idea of what standard TTL logic levels are, but why the qualification?  Can I use the 74HC14 to directly drive these inputs, or do I need to use an open drain or collector pulled up to +12V?  What are the actual hi and lo voltage thresholds?

Thanks,

Mike