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PCM5121: PCM5121: SCK (MCLK)

ARIAKE Yoshiaki
Intellectual 430 points
Part Number: PCM5121
Other Parts Discussed in Thread: CC1310

Hi,

I connecting PCM5121 and CC1310 by I2S.
CC1310 config is below:
BDIV = 75
MDIV = 38 (MCLK = MCUCLK/MDIV [Hz])
WDIV = 0x2020 (WCLK = MCUCLK/(BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz]))

Does not work PCM 5121.
But, it work when stopped MCLK.

PCM5121 config is below:
XSMT = 1 : soft un-mute
MAST = 0 : I2S SLAVE(BCK/LRCK inputs)
MODE[1:2] = 00 : HARDWIRED MODE
FMT = 0 : I2S
DEMP = 0 : De-emphasis control off
ATT[2:0] = 000 : GAIN AND ATTENUATION LEVEL 0dB
AGNS = 0 : Analog Gain 0dB 2Vrms
FLT = 0 : Normal latency

Do I need to set up MCLK(SCK) inputs.

  • 0
    TI__Guru 57800 points

    Hi,

    The described behavior suggests that the device is having issues when MCLK is provided, what is the frequency of MCLK?. The PCM5121 enters in normal operation mode automatically when all clocks are valid, but when MCLK is at ground level for 16 successive LRCK periods, the device could work normally as internal clocks will be generated from from BCLK. This suggests that MCLK signal provided is not valid. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 430 points

    Thanks for your reply.

    MCLK is what CC1310 was generate (MCUCLK by CC1310: 48MHz / MDIV: 38 = 1263157.8947...Hz).


    You mean, PCM5121 could work normally without MCLK?

  • 0 in reply to ARIAKE Yoshiaki
    TI__Guru 57800 points

    Hi, 

    The PCM5121 can operate in a 3-wire mode (no MCLK) by generating the internal clocks from the BCLK on systems where MCLK is not available. For more information on this operation mode, please refer to section 8.3.6.3 of the datasheet. The clock from your controller is not compliant with the required MCLK rates for the device, please refer to Table 32 for the detailed MCLK ratio support.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Intellectual 430 points

    Should not we Input MCLK in the case of 10.000 kHz sampling rate?
    Should we input MCLK in the case of sampling rate described Table 32?

  • 0 in reply to ARIAKE Yoshiaki
    TI__Guru 57800 points

    Hi,

    System Clock (MCLK) input should match the specified rates described in table 32 for a proper operation of the device. Otherwise, if a MCLK with valid rates can't be provided, 3-wire I²S operation is recommended.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer