TAS5719: Asking for the TAS5719 bypass cap design concern

Hi Team,
Add questions from customer.

1. Ripple and noise requirement? For example: 500mVp-p @20MHz?
2. In order to prevent audiable noise, we should specially watch the frequency band of noise from 1Hz to 25KHz, right?
3. What is the minimum ESR and ESL requirement? As you see, the ripple & Noise will be dominated by Cap ESR, ESL and loading current slew rate and step, if we just want to meet the 220uF requirment, then IEC will propably just place Electrolytic capacitor with a hurge ESR and ESL, in current schematic design that IEC is using 3 pcs polymer caps with very low ESR( 2x mohm), this should be able to provide better power quality.
4.If possible, could you provide these parameter, then we can investigate more on this before PCB release.
5. Is this a closed loop digital Amp? So it should have more better ripple rejection, right?
6.Require any input choke? And value

Do we have application note to explain the selection for the bulk 220uF cap? Or how stable the power can allow use small bulk cap on PVDD.

Thanks,
SHH

Hi Scott,

Can you please link me to the reference design you are referring to? I don't see reference to a 220uF cap in the datasheet or a reference design for the 5719

Regards,

Alex

Hi Alex,

Please refer to the EVM user guide.

Thanks,

SHH

Hi SHH,

The EVM takes input from a power supply into the banana cable input. Since the power supply is unknown with the EVM the decoupling has to be conservative, hence the 220uF cap. Please refer to pages 20 and 58 of the datasheet for guidelines on choosing decoupling cap values. 220uF cap is not mentioned there.

2) Audible noise is 20 to 20,000 Hz.

5) It is an open loop amp

1,3,4,6) It sounds like most of your other follow up questions were contingent on needing the 220uF cap. Please let me know if the customer still has questions about them now that they do not need this cap and I can look in to them further. Also I would need the schematic to answer some of them.

Regards,

Alex

Hi Alex,

For customer's PCB, how to determine the bulk cap values?

For page58, I believe it is use for the headphone bulk cap. Can you confirm?

Thanks,

SHH

Hi SHH,

The decoupling cap section on page 58 is for the PVDD power supply pin, which is used for the speaker outputs.

This app note www.ti.com/.../slyt199.pdf has a good section the describes the design process for determining bulk capacitor values. Please let me know if you have any question about this.

Regards,

Alex