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PCM1865: PCM1865 PLL locking problems

Skirmantas Lauzikas
Prodigy 30 points
Part Number: PCM1865

Hello,

I'm having a hard time getting PLL to lock,
the MCLK source for PCM1865 is a 12MHz 50ppm oscillator, then configuring PLL I do see the expected frequencies on SCK/BCK/LRCK pins, but no lock (reg 0x28 b4)
Config for Fs 48000:
pll: k = 8.1920  p=1 r=1, dsp1: 4, dsp2: 8, adc: 16, sck: 8, bck: 4, lrck: 64

Full registry dump:
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 00 00 00 00 86 41 41 42 42 00 4c 00 00 00 00
10: 30 52 44 40 00 f0 00 00 00 00 00 00 00 00 00 00
20: 7e 03 07 0f 50 07 03 3f 01 00 00 08 80 07 00 00
30: 00 00 00 01 00 00 01 00 00 00 00 00 00 00 00 00
40: 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80
50: 7f 00 80 7f 00 80 7f 00 00 00 00 00 00 00 00 00
60: 01 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 70 10 0f 03 32 00 11 c4 07 00 00 00 00 00 00 00
80: 00 00 00 00 00 86 41 41 42 42 00 4c 00 00 00 00
90: 30 52 44 40 08 f0 00 00 00 00 00 00 00 00 00 00
a0: 7e 03 07 0f 50 07 03 3f 01 00 00 08 80 07 00 00
b0: 00 00 00 01 00 00 01 00 00 00 00 00 00 00 00 00
c0: 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80 7f 00 80
d0: 7f 00 80 7f 00 80 7f 00 00 00 00 00 00 00 00 00
e0: 01 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 70 10 0f 03 32 00 11 c4 07 00 00 00 00 00 00 00

There were similar problems discussed in this forum previously, but in my case, PLL wont lock even with config sequences provided there (values adjusted for 12MHz clock):

i2cset -y -f 1 0x4a 0x00 0xFE
i2cset -y -f 1 0x4a 0x00 0x0

i2cset -y -f 1 0x4a 0x25 0x7
i2cset -y -f 1 0x4a 0x26 0x3
i2cset -y -f 1 0x4a 0x27 0x3F

i2cset -y -f 1 0x4a 0x20 0x7E
i2cset -y -f 1 0x4a 0x28 0x01

i2cset -y -f 1 0x4a 0x21 0x03
i2cset -y -f 1 0x4a 0x22 0x07
i2cset -y -f 1 0x4a 0x23 0x0F

i2cset -y -f 1 0x4a 0x29 0x00
i2cset -y -f 1 0x4a 0x2a 0x00
i2cset -y -f 1 0x4a 0x2b 0x08
i2cset -y -f 1 0x4a 0x2c 0x80
i2cset -y -f 1 0x4a 0x2d 0x07

Am I missing something?
Also, is there any ETA for the new revision of datasheet?

  • 0
    TI__Guru 57800 points

    Hi, Skirmantas,

    The register configuration seems correct for a Master mode, PLL clock from non-standard SCKI input mode. I tested this and it seems that when writing a '0' to PLL lock bit, the device is not reporting back the lock status until a '1' is written. After this, the PLL lock bit will remain in '1' until the PLL gets unlocked by any reason.

    Best Regards,

      -Diego Meléndez López
        Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 30 points
    Tested this, and it seem the procedure is:
    1. enable PLL by writing 0x01 to register 0x28
    2. write 0x11 to register 0x28
    3. check if lock bit is holding, if not, pll hasn't yet locked, go to step 2.

    Interestingly, the lock bit is being set then PLL gets disabled...