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TLV320AIC3110: TLV320AIC3110

Brijesh kathavadia
Prodigy 120 points
Part Number: TLV320AIC3110

Hello, 

Is it mandatory to Provide MCLK to TLV320AIC3110 Audio Codec ?

As i have seen in Datasheet functional Block diagram of Codec there is note : 

Normally, MCLK is PLL input; however, BCLK, GPIO1, etc., can also be PLL input.

But  as I2s signal we already providing BCLK then again why we need to provide MCLK to codec ?

Brijesh.

  • 0
    TI__Guru* 84915 points
    Hi, Brijesh,

    The MCLK is required when the codec works in master mode (BCLK and WCLK as outputs). If the audio codec is configured as slave, the MCLK is not required. However, you need a PLL source in order to generate the internal sampling rate and other clocks. So, if MCLK is not being used, BCLK and GPIO1 can work as PLL clock source.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0
    Prodigy 120 points

    Hello,


    I need support to know whether TLV320AIC3110 requires power up/ down sequence or not?
    Regards,
    Brijesh Kathavadia
    Engineer | PES Hardware - eInfochips
    Cell: 9714905689
      


  • 0 in reply to Brijesh kathavadia
    TI__Guru* 84915 points
    Hi, Brijesh,

    The TLV320AIC3110 and the most part of our audio codecs require to separate digital from analog activity in order to get the best performance in the codec. So, you would need to power up first the digital power supplies (DVDD and IOVDD). Once the power supplies are stable, you would need to power up the analog power supplies (AVDD, HPVDD, SPLVDD, SPRVDD).

    Additionally, I recommend to separate the digital and analog ground into two planes. Digital ground plane contains DVSS and IOVSS. Analog ground plane contains thermal pad, HPVSS, AVSS, SPRVSS and SPLVSS. Both planes must be joined with a 0-ohm resistor or a trace line. This will help for noise immunity.

    Best regards,
    Luis Fernando Rodríguez S.