TAS5719: Question of MCLK and BCLK for the TAS5717/TAS5719

Wayne Chen (ex FAE)

Part Number: TAS5719
Other Parts Discussed in Thread: TAS5717,

Hi Sirs,

The TAS5717/TAS5719's MCLk and BCLK input must be aligned with each other as we know.
Would you pls advise if we can make them align on falling edge as the picture below?

Thank you and Best regards,

Wayne Chen
09/07/2017

over 6 years ago

0 Jeff Kohnle over 6 years ago

TI__Expert 6985 points

Hello Wayne! Just so I am clear on your question, as a slave device you only have the MCLK feeding into the TAS5717/9? What are you doing with the BCLK... do you mean SCLK (bit clock) per the datasheet? Please reference: e2e.ti.com/.../2425.i2s-clock-requirements-on-tas570x1x2x3x-device-s Thanks, Jeff

0 Wayne Chen (ex FAE) over 6 years ago in reply to Jeff Kohnle

Guru 15950 points

Hi Jeff,

Thank you for your concern. Customer use CPU's GPIO to send MCLK and BCLK. Their frequencies can meet TAS5719's specification, while their MCLK and BCLK can align at falling edges. The TAS5719 is functional now, but we don't now if we have potential problem with this behavior.

Wayne Chen
09/08/2017

0 Jeff Kohnle over 6 years ago in reply to Wayne Chen (ex FAE)

TI__Expert 6985 points

Hello Wayne! You shouldn't, but lets also have Shawn take a look at this.

Hello Shawn! Do you see any issues with alignment on the falling edge of the MCLK?

Thanks, Jeff

0 Wayne Chen (ex FAE) over 6 years ago in reply to Jeff Kohnle

Guru 15950 points

Hi Jeff,

Thanks a lot. Did you mean that we can only make MCLK and BCLK aligned on rising edges for TAS5717/19?

Falling Edge:

Rising Edge

Thank you and Best regards,

Wayne Chen
09/11/2017

0 Shawn Zheng over 6 years ago in reply to Wayne Chen (ex FAE)

TI__Mastermind 24835 points

Hi Wayne,
For the first case(MCLK and SLK aligned on the falling edge), it's not a typical application usage.
How much is the input I2S sampling rate(44.1MHz/48kHz?) and the word withdth(32bits?)? If SCLK is in the range of 2.8224MHz ~ 24.576MHz, you can use the SLCLK signal for MCLK. In this way, you don't need to generate a MCLK signal on host side. I believe this is the simplest way.
Best regards,
Shawn Zheng

0 Wayne Chen (ex FAE) over 6 years ago in reply to Shawn Zheng

Guru 15950 points

Hello Shawn,

Thank you for your concern. Customer use 32 bit I2S pad with 16kHz sample rate thus we are not able to connect MCLK and BCLK together. We found that the TAS5717/19 is functional with MCLK and BCLK aligned on falling edge. However, we will suggest customer not to do it (although it is CPU's limitation) if there is technical concern from product line.

Thank you and Best regards,

Wayne Chen
09/11/2017

0 Shawn Zheng over 6 years ago in reply to Wayne Chen (ex FAE)

TI__Mastermind 24835 points

Hi Wayne,
From our designer's point of view, this configuration should work functionally. But we don't have much measurement data for it actually, due to it's not a typical application. So we can't make sure the stability/reliability with this configuration.
Best regards,
Shawn Zheng

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TAS5719: Question of MCLK and BCLK for the TAS5717/TAS5719