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TAS6422-Q1: I2S without MCLK

Teun Kloosterman
Prodigy 20 points
Part Number: TAS6422-Q1
Other Parts Discussed in Thread: CDCS503

I would like to use the TAS6422 in a design, but wouldn't like to have an external oscillator with clock divider for MCLK/SCLK.

Unfortunately, I don't really understand the datasheet when it comes to MCLK. There's no mention of MCLK outside the TDM mode configuration. Since I want to use I2S, it is not specified how the MCLK pin behaves.

Is it okay to leave open / connect to ground?

Or can I connect MCLK to SCLK for 64 x fs operation?

What does: "The MCLK clock must not be in phase to sync to SCLK." mean? Must not? May not? Doesn't have to be?

I did see some old posts, but don't know if they still apply today. Thanks for your support.

  • 0
    TI__Expert 6985 points
    Hello Teun! The TAS64xx devices do require a MCLK from the processor or you can use a PLL (e.g. CDCS503) which can create a MCLK from the SCLK. Also, please note that while the M/SCLK pins can be connected that the TAS64xx's do not support MCLK = 64Fs & SCLK = 128Fs is also not supported.
    Please reference the Datasheet section: 9.3.1.5 Supported Clock Rates; The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS & The device supports SCLK rates of 32 or 64 × fS in I2S, LJ or RJ modes or 128 × fS, or 256 × fS in TDM mode.

    Hello Tuan! Can you please elaborate on "What does: "The MCLK clock must not be in phase to sync to SCLK." mean?" ...as this statement is a bit confusing. To me it reads as they do not need to be in sync. Thanks, Jeff
  • 0 in reply to Jeff Kohnle
    Prodigy 20 points

    Hi Jeff, thanks for your reply!

    I already guessed I wouldn't get off that cheaply :)

    So, just to check if I understand this right...
    For 24 bit 96 kHz stereo audio, the FSYNC = 96 kHz, SCLK = 64 FS and MCLK = 256 FS.
    This means I can use a CDCS503 with 4x multiplier from SCLK to MCLK.
    SCLK = 96kHz * 64 = 6.144 MHz
    MCLK = 96kHz * 256 = 24.576 MHz (which is less than 25 MHz)

    I would guess the SSC is better left disabled to prevent corrections for jitter/flutter by the multiplier actually causing errors in the TAS6422, would you agree?

    The statement is a bit arbitrary, I copied it from the datasheet paragraph 9.3.1.5 page 19:
    "The MCLK clock must not be in phase to sync to SCLK. Duty cycle of 50% is required for 128x FSYNC, for 256x
    and 512x 50% duty is not required"

    So I guess I don't have to correct this setup for phase anyhow.

  • 0 in reply to Teun Kloosterman
    TI__Expert 6985 points
    Hello Tuan! Could you please double check the above?

    thanks, Jeff