Our customer is facing issue of "No sound output" after Power Save Mode in PLL operation mode.
On datasheet page33 there is description as below.
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When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start
correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup
sequence automatically.
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My concern is if I2S data rate is changed before and after of "Power Save Mode", in that case, PCM510x can automatically re-synchronize and powerup? Or PCM510x will waiting expected rate I2S clock input.
In other word, to re-synchronize to new rate of I2S input, Is Vdd power down reset required?
Regards,
Mochizuki
