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TAS5713PHPEVM: minimize latency from digital input to analog output

Part Number: TAS5713PHPEVM
Other Parts Discussed in Thread: TAS5780M, TAS5782M, TAS5713

Dear sir or madam,

we are testing the TAS5713PHP EVM Board and recognized a latency of approx. 30 cycles at 8 kHz. Unfortunately this is way too Long for our application. I already disabled the biquad filters and set the interchannel delay registers to Minimum delay. Still 30 cycles. Is their any way to minimize the group delay? Or do we have to choose a higher sampling rate to optimize it?

Unfortunately the datasheet says nothing about the group delay of the amplifier.

Best regards

Marc

  • Hi Marc,
    If you already disabled all of the digital processing(e.g. BQ, DRC...), I think there is no other way to decrease the delay. You are right, the delay can be minimized by using a higher sampling rate. TAS5713 supports up to 48kHz sampling rate input. You could also check TAS5780M/TAS5782M, which supports up to 96kHz sampling rate input.
    Best regards,
    Shawn Zheng
  • Dear Shawn,

    thanks for the fast feedback. But I am really wondering if a delay of > 20 LRCLK samples seems to be valid for this amplifier. I would expect a delay of max. 5 LRCLK samples. Nevertheless I have no reference since there is no hint in the datasheet what latency should be right.

    Best regards

    Marc

  • Hi Marc,
    Generally more than 20 LRCLK delay is expected for a digital input audio amplifier. Even BQ and DRC are disabled, there are also some logic delay inside the deivce(e.g. after digital processing, there is FIR block which up-sample the signal from 48kHz to 384kHz/768kHz, it usually causes more than 20 LRCLK delay). Less than 5 LRCLK delay looks not quite possible for a digital input audio amp for now. And 5 LRCLK is only around 0.1ms, which is quite short and far out of human perception.
    Best regards,
    Shawn Zheng