Hi there,
I want to use the TAS5601 with a modulator in a FPGA. However - I want to use higher switching frequencies than the max. specified 400 kHz in the datasheet.
Is this a problem? (e.g. internal logic will recognize and shutdown)?
Thanks!
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Hi there,
I want to use the TAS5601 with a modulator in a FPGA. However - I want to use higher switching frequencies than the max. specified 400 kHz in the datasheet.
Is this a problem? (e.g. internal logic will recognize and shutdown)?
Thanks!
Hi Adam,
thank you for your reply.
My goal would be 500 kHz. In case you are wondering why exactly I want to use this frequency -> I want to use a finished IP core for the modulation and this is fixed between min. 500 kHz and max. 750 kHz.
How is it possible to turn off the closed-loop? I don't think that you can hear it so much - because all distortion generated by limited rise/fall time of the bridges and not ideal PWM will be seen common-mode by the speaker and is cancelled out.
But also one further question regarding the closed loop:
In my understanding the loop has to regulate against two points:
- Voltage-drop of input voltage at high currents peaks (when for short time a lot of power is needed (e.g. short bass pulses)
- due to limited rise-fall time of the output bridges the original PWM-signal is changed somehow. So the loop has to integrate over on and off period at the output and compare against the incoming pwm.
Is my understanding correct?