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Original question:
Hello TI E2E Community,
I have one question regarding the TDM format. I am using two PCM1865 connected together at one DOUT line for 8CH TDM. The first one has no offset and the second one has an offset of 128. Both ADCs are running as slave because I have an external clock-source. First of all, I can receive all 8 channels and the signal seems to be right, but there is one confusing part. I am not 100% sure at which BCK the PCM1865 clocks out the data in TDM mode.
- Is it clocked out like Left-Justified (on the first BCK) or is it clocked out like I2S with one BCK delay?
When I select I2S mode in the receiver, everthing works fine until you come to an input voltage of about 1.5Vrms. The signal is distorted if I am using higher voltages, but the limit should be 2.1Vrms. You can see in the second picture that the ADC is not overdriven, so this seems to be an Bit-Overflow.
When I select Left-justified mode in the receiver, everthing works fine. Also until 2.1Vrms input voltage. But as you can see the signal is reduced compared to I2S mode. Of course, if this is the right configuration, this is the real value, but I am not sure.
Could you explain me what is the right configuration for the receiver BCK (Left-Justified or I2S).
Best regards and many thanks in advance,
Eric
