• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 252 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPA3144D2: Asking for the TPA3144 schematic and layout review

SHH
Mastermind 30856 points
Part Number: TPA3144D2


Hi team,
Would you please review the TPA3144 schematic and layout?

the output power request is 3W/8ohm. I will suggest customer to use the following setting.
1.PVCC=7.5V
2.Gain=36dB
3.LIMRATE=fast
4.LIMTHRES=1.193V
5.SSCTRL=SS OFF1
6.GVDD=6.91V. (it is from TPA3144 itself)
7. max input gain, limit to 320mV

Here is the schematic and layout file.
txn.box.com/.../5k4xpcxni0j98nluamacrxhhr0zrsfor

BR,
SHH

  • 0
    TI__Mastermind 24835 points

    Hi Scott,

    I'm not quite sure the voltage setting is correct on the following pins: GAIN, SSCTRL...

    If Gain is set to 36dB, the voltage on GAIN pin should be GVDD.

    If SS is disabled, the voltage on SSCTRL should be connect to GND.

    When the input signal is as large as 320mV, the output signal could reach 20.48V and hard clipping occurs.

    Please use higher impedance ferrite beads(e.g. 300Ohm at 100MHz) in the output filter to achieve better EMI performance.

    Input is single-ended mode, please use pseudo-differential routing for the input traces to improve pop noise performance - the INP input signal trace is very long on the board.

    Best regards,

    Shawn Zheng