Original question:
Hello,
I'm trying to connect my EVM 2770 board via I2S to the I2S output of my device. I did connect properly the FSYNC, SDIN, SDOUT, and CLK signals to the board. Now how do U switch the board from "USB audio" mode to I2S audio mode? Any specific jumpers to be set? I did put FSYNC jumper on J1, but still I get no audio. Anything to toggle from PPC3?
Cheers,
Alex
Hi Ivan,
Sorry, I meant J11, not J1
The external TDM source is connected to J7 correctly (I hope)
J2 is even now
(in USB mode) not connected
Cheers,
Alex
Hi Ivan,
I have this entry in my device tree (Allwinner H3 SoC)
pcm5102a: pcm5102a {
#sound-dai-cells = <0>;
compatible = "ti,pcm5102a";
status = "okay";
};
sound_i2s {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "ti,pcm5102a";
simple-audio-card,mclk-fs = <256>;
status="okay";
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,codec {
sound-dai = <&pcm5102a>;
};
};
The tests I do as:
speaker-test -D plughw:CARD=tipcm5102a -r 44100 -c 2 -F S16_LE -f 2000 -t sine
In this case i get a noisy audio.
What I can see from the scope is:
- Bitclock is around 2.8MHz that makes sense
- the FSYNC is 23-4 us, ie arounf 44kHz, which corresponds to SBCLK/FS ratio 64 ?
- The data are present on one channel only-even if I have set 2 channels
- The data are sometimes received during the "non-active" (high) state of the FSCLK
The EVM is set to autodetect the SR and SBCLK/FS ratio. If I set them off, I gave to set 44.1 SR and SBCLK/FS = 64 to have audio
The TDM is set to trigger on Falling edge of SBCLK, left justified. High to Low onFSYNK, 16 bits word length, 32 bit slot, selecting mono left channel only.
Do you see something wrong?
Hi Ivan,
I'm sending the two photos-one of my setup, described in my previous message, and the one from the USB chip of the EVM board.
The output from the USB chip is with FSCLK 48kHz, SBCLK 12,288 MHz, SBCLK/FSCLK ratio 256. One main difference: FSCLK is with a short pulse, while the others have 50% duty cycle. Also the signal is noisy, but it works. One more detail-as soon as I connect the GND of the scope probe, the audio becomes with clicks (The scope picture is with the probe GND attached, without it is even more noisy). But this could be an issue with the scope's ground. 
Hi Ivan,
Thanks to your recommendations, now we have one of the devices (the one that is providing 16bit samples, with 16 bit slot size, running at 48kHz SR. The picture on the scope is similar to yours, but recalculated for 48kHz.
However, the other HW audio module that provides 16 pis samples on 32 bit slot (48 kHz) is a bit noisy on the EVM board. I have tried all possible settings in EVM, but could not make it work. Here are my settings:
I2S audio:
SR=48 kHz, FSCLK=48 kHz. SBCLK=3,072MHz, SBCLK/FSCLK ratio = 64
EVM settings
PLAYBACK: Sample Rate=44.1/48 kHz, Sample Ramp Rate=48kHz, SBCLK/FS Ratio =64,
TDM: Edge Polarity = Rising Edge of SBKLK, Left justified, Frame Start Polarity = High to Low on FSYNC, Word length=16 bit, Slot length=32 bit, receiver Offset=1
On the picture one channel is not shown because I'm using speakertest:
speaker-test -D plughw:CARD=tipcm5102a -r 48000 -c2 -f 2000 -t sine
which alternates the channels
Do you have an idea what we are doing wrong on the EVM configuration?
Cheers,
Alex
Alex,
The "Sample Ramp Rate" allows you to select the base multiple of your frame clock. Depending on the setting of "Sample Rate":
The selection in Sample Ramp Rate of 44.1 kHz will set the device for the lower frequency in each of the above settings.
"Receiver Offset" is in bits. Standard I2S has a 1 bit offset. This can be adjusted to match whatever format the data is being sent. If this doesn't match the source, audio can easily become distorted, but you will not observe any clock errors. It will just interpret the input data with the MSB starting in the wrong location.
IRQ is an interrupt flag setting. There is a device pin that will output either High or Low depending on the device settings. This may be used as an input to the host to indicate an error such as a clock fault. Additionally, within PPC3, the user is able to read back either latched or live fault flags. Typically, the host would read this fault back after the IRQ pin toggles and take appropriate action to handle the fault. For errors with Frame/Word Clock or with Bit Clock, we can check the latched flags after powering up the device. Given any mismatch between device clock settings and the input source, I would expect to see the device enter shutdown immediately and to see the "TDM Clock Error" flag assert. To check the flag, click the IRQ button and then click "Read". If any fault condition is read back, the grey circle will illuminate orange for the corresponding flag. This is a self clearing register, so a second read will show this being reset.
For the case you suggest of a 44.1 kHz input at a 16 bit word, and a SBCLK clock ratio of 32 I would set the device as shown below:
Having the offset set to '1' here will expect the MSB of the data to be the second bit following the falling edge of frame clock. This is typical case for I2S, but your source may be transmitting with no offset.
Hi Scott,
Thanks for your nice explanation, I was wondering what this "Sample Ramp Rate" means. now is clear.
About the settings you propose-yes, it is exactly these that do work with our other audio module, that provides 16 bit samples on 16 bit slots, 44.1kHz. THE EVM board plays this i2s format just fine.
On the contrary, the EVM cannot sync to our new audio module, that provides 16 bit samples, 32 bits slot, 48kHz. Whatever settings I do put in the EVM, I have always noise, and TDM Clock error on the IRQ values.
What it makes it even more confusing is that the TDM_DET register is 0x23, which is what I would expect: ratio=64, and SR-48kHz. Then where this "TDM Clock Error" is coming from?
I'm sending you a snapshot of my scope to see the data format-you can see that it is a perfect i2s format.
Cheers,
Alex
Alex,
The IRQ "TDM Clock Error" flag is read from register 0x24 bit 2. I've tried to recreate your setup:
I likewise read back 0x23 from register 0x77. I am able to play a continuous sine tone that does not sound distorted with the settings below. I am transmitting with a 1 bit offset and have the device set to receive the same:
If with these settings you still get clock errors, I would check the quality of the I2S signal on the EVM. Was your scope capture taken on the EVM? Typically it is best practice to add a GND return for each signal when pairing clocks from one system to another. Without a sufficient GND return the data will easily become corrupted.
Also, please be sure that your input logic levels match the expected levels on the EVM. Jumper J1 for VCC select - I2S will set the expected input voltage. If you have it set to 3.3 V and are driving with 1.8 V, it may not latch the incoming data correctly.
It may be that since the device recognizes the clock frequencies that you are just getting random glitches that trigger the clock error.
Hi Scott,
One update: today we have received another TAS2770YFFEVM board, and tried with it. The result is the same-still noisy output, which might mean that the audio comes already distorted from our audio module. Will dig in that direction in the first days after Christmas. I also did make a screenshot of the scope, this time measuring directly on the i2s output of our module instead on the control points of the evaluation board. It is the same, no difference.
For me the format is:
16bits sample, 32 bit slot, x64 ratio, trigger on high-to-low of frame clock, 1 bit delay. latch the first data bit on falling edge of bitclk.
However does not work neither with these settings, nor with any other combination
Thank you very much for your support, and have nice Christmas holidays,
Cheers,
Alex
