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Hi, Team,
May meet some problem during testing 6424-Q1:
BACKGROUND:
Our project uses TAS6424QDKQRQ1 power amplifier, the schematic diagram is as attachment. When playing 1K audio at maximum volume, an abnormal output will occur, the waveform is as follows:
output abnormal
Our customer link the MCLK to SCLK.
From testing, we found that the abnormal output is related to MCLK linked with SCLK. When we disconnect MCLK and SCLK and supply MCLK separately, the output abnormality disappears.
QUESTION:
1)In our schematic diagram, short-circuiting MCLK and SCLK together is as described in the reference specification 9.3.1.4. Does this power amplifier have this kind of usage(short-circuited MCLK and SCLK together) in other customer projects? Do they have similar problems?
2. DS 9.3.1.4 in the specification describes "The MCLK clock must not be in phase to sync to SCLK". If MCLK and SCLK are short-circuited, how can the two clocks be in different phase?
BR
Brandon Li
Zhanpeng,
When MCLK tied to SCLK in TDM mode, please use 1 slot pulse width for FSYNC pin. we can email or phone discuss to talk about more details.
BTW, i see PVDD voltage is 14.4V, not boosted appliaciton, is that correct? if so, another option is to use TAS6424LS-Q1 device.
Dylan