• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 605 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

OPA1644: OPA1644 failure

CLAVERIE Alain
Intellectual 410 points
Part Number: OPA1644

Hi 

We 're facing a problemewith the following design 

The 2 OPA1644 fails and when analysing their 15 V PWR supply is nearly ins CC (the PS fails)

Whe think that the problem comes from that it" possible tue conected card to the 2 inputs can be powered on when this part of our card is not powered on

The inputs can raise signals between 0 and 10 V while our design is not powered !

could you confirm our analysis ?

Have you an idea how to protectt our inputs ? (a relay  dcontrolled by PS in serie is difficult to insert for us in design)

Thanks

Regards

  • 0
    TI__Guru* 93105 points

    Hello Claverie,

    Have a look at Section 8.1.7, Electrical Overstress, in the OPA1644 datasheet. Figure 38, Equivalent Internal ESD Circuitry and the Relation to a Typical Circuit Application, shows the internal ESD paths internal to the OPA1644 that could be subject to EOS damage if precautions aren't taken to limit the input current.

    One of easier ways to protect the inputs from damage should an EOS condition occur is to provide input current limiting. That is most easily accomplished by adding a resistor in series with the op amp input where the over-voltage might be applied. Figure 38 shows this resistor as Rs, which is applied to the non-inverting input. Certainly, the higher in value this resistor can be made the more effectively the current limit will be for a given voltage. However, the resistor does add thermal noise which is undesirable in a low-noise application.

    I often recommend an Rs on the order of 1 kilohm for an EOS voltage of about 10 V, but that may add too much thermal noise. Dropping the resistor down to a few hundred ohms might be enough to provide sufficient protection. Additionally, I do recommend adding the TVS diodes shown in Figure 38 as they provide a voltage clamp and current path during an EOS event.

    By the way, OPA1644 U48A and U61B must have an input bias current return path to ground. The schematic as shown does not provide that unless the D89 and D111 are leaky enough to provide the return paths. If the board IN+ and IN- pins terminate in external resistors that connect to ground, then they would provide input bias current return paths.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • 0 in reply to Thomas Kuehl
    Intellectual 410 points

    Hi 

    First many thanks for your reply 

    Juste to be sure well understand

    Adding 1K resistor will provide protection for ESD problem .. I understand that they will also provide protection inVS+and VS- are 0 V by reducing input current  (right ) ? 

    The TVS diode is ONLY ??? for protection of hig PS voltage so if I 'me sure that inputs never over 10 V I car avoid them ? or are they also acting for ESD pb  ?

    Last thing ... I don't really understad 

    "PA1644 U48A and U61B must have an input bias current return path to ground"

    Does ti mean that I must add resistors in parallel of D89 and D111 diodes ? 

    Regards

    Alain

  • 0 in reply to CLAVERIE Alain
    TI__Guru* 93105 points

    Hello Alian,

    Regarding your questions:

    Adding 1K resistor will provide protection for ESD problem .. I understand that they will also provide protection inVS+and VS- are 0 V by reducing input current  (right ) ? 

    Actually, the OPA1644 has built-in protection for out-of-circuit ESD events such as those that can occur during handling and assembly. The 1 k resistor I recommend adding is for in-circuit electrical overstress (EOS) protection. It works by limiting the current that can flow in the input circuit during an unexpected EOS event. Even if the OPA1644 input circuit could fully conduct the current with a 10 V EOS would be limited to 10 V / 1 k, or 10 mA. The ESD cells can handle that current without damage.

    The TVS diode is ONLY ??? for protection of hig PS voltage so if I 'me sure that inputs never over 10 V I car avoid them ? or are they also acting for ESD pb  ?

    The TVS diodes in this case can provide supply pin EOS protection, but can also provide a current return path for the input current during an input EOS event. The OPA1644 ESD diodes connect from each input to each supply pin. If the EOS voltage applied to the input is high enough, the ESD diode becomes forward biased. The current then flows through the ESD diode to the supply pin. It needs to find a return path to ground. If the TVS becomes activated by the EOS event voltage it provides that path and limits the voltage at the supply pin.

    Last thing ... I don't really understand 

    "PA1644 U48A and U61B must have an input bias current return path to ground"

    Does ti mean that I must add resistors in parallel of D89 and D111 diodes ? 

    If the input sources driving IN+ and IN- do not provide a dc return path to ground for the op amp input bias current, then yes a resistive path must be provided. Since the input bias current are extremely low the input resistors to ground can be very high in value. However, the lower they can be made the better from a current noise consideration. Current noise flows through the resistors and is converted to voltage noise which adds to the overall noise.

    Regards, Thomas

    Precision Amplifiers Applications Engineering

  • 0 in reply to Thomas Kuehl
    Intellectual 410 points

    Hi 

    Many thanks !

    Alain