Hello,
My customer has been investigating PCM1808-Q1. They'll use the same circuit as shown in figure 26. In this case, the inputs of AND aren't synchronized, so glitch can happen at SCKI pin when /MASK signal works(L->H, H->L) which may not meet the requirement of the datasheet. What would happen in this case? It should be OK since the figure 26 is shown in the datasheet, but please let me confirm how it works in this case. Or does /MASK signal has to be stable before the PLL is enabled or disabled to have variable output?
Best Regards,
Yoshikazu Kawasaki