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PCM1808-Q1: How does it work if the SCKI pulse width doesn't meet the datasheet by the glitch from the AND gate shown in figure 26?

Yoshikazu Kawasaki
Expert 3510 points
Part Number: PCM1808-Q1

Hello,

My customer has been investigating PCM1808-Q1.  They'll use the same circuit as shown in figure 26.  In this case, the inputs of AND aren't synchronized, so glitch can happen at SCKI pin when /MASK signal works(L->H, H->L) which may not meet the requirement of the datasheet.  What would happen in this case?  It should be OK since the figure 26 is shown in the datasheet, but please let me confirm how it works in this case.  Or does /MASK signal has to be stable before the PLL is enabled or disabled to have variable output?

Best Regards,

Yoshikazu Kawasaki

  • 0
    TI__Mastermind 23050 points

    Hi Kawasaki-san,

    Which requirement are you referring to? The MASK signal does not need to be synchronous with SCKI and should basically be used as an enable function. You keep it high to pass SCKI through and pull it low to halt the SCKI. Refer to figure 20 for the clock-halt power-down and reset timing. It takes approximately 4us once SCKI is halted until the device initiates a reset and pulls data low.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 3510 points

    Hello Zack,

    Thank you very much for your quick reply.

    I referred to figure 26 on page 19 in the datasheet.  I know SCKI doesn't have to be synchronized with /MASK.  I meant /MASK and output of PLL170x aren't synchronized.  Therefore the output of the AND gate can have glitch which goes to SCKI when /MASK signal moves 1->0 or 0->1 while PLL170x output is active.  That's what my customer is worried about.

    Does the figure 26 expect /MASK to be stable while PLL170x output is active like this?  Otherwise the output of AND has glitch and SCKI receives the glitch.  Or can SCKI receive glitch by /MASK change while PLL170x output is active that PCM1808-Q1 will output data from DOUT by the glitch though?

    ● Power up the system

    ---> /MASK=L and PLL170x is low which is in clock-halt reset state

    ---> /MASK=L->H

    ---> PLL170x enabled (output is active)

    ---> Output of AND is active (SCKI receives clock)

    ---> /MASK mustn't move H->L or L->H again?  Or /MASK can move?

    ● Power down the system

    ---> Output of AND is active (SCKI receives clock)

    ---> /MASK mustn't move H->L or L->H again?  Or /MASK can move?

    --->  PLL170x disabled (output is inactive)

    ---> /MASK=H->L

    ---> /MASK=L and PLL170x is low which is in clock-halt reset state

    Best Regards,

    Yoshikazu Kawasaki

  • 0 in reply to Yoshikazu Kawasaki
    TI__Mastermind 23050 points

    Hi Yoshizaku,

    The MASK bit acts as an enable/disable, this signal can be toggled as necessary to halt or resume the output. The data will output until slightly after SCKI is halted and then it will go to zero. There is no fade out operation with this, it is abrupt so your customer may need to consider this when stopping the clock and mute anything, such as an amplifier, that might be relying on the data output. This is not a glitch on SCKI though as this is how the device is intended to operate. The mask bit should not oscillate between values though as this could cause a potential glitch and may appear as a loss of synchronization rather than a halting of SCKI, during which there may be data but it will be undefined data. So if the MASK bit is toggled you should wait at least until data goes low or comes back high before it is toggled again to avoid abnormal operation.

    Best,

    Zak