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DIT4096: MCLK and SCK timing in Master mode

Mochi
Genius 3885 points
Part Number: DIT4096

Hello,

 

Our customer plans to share DIT4096 inputted MCLK to their DSP system, in this case the DSP required some timing specification of Input MCLK clock between outputted SCLK and SYNC.

Usually we can see such clock timing specification in Master mode on Audio interface device.

This is urgent device replacement activity.

 

Regards,

Mochizuki

  • 0
    TI__Mastermind 23050 points

    Hi Mochi,

    The timing of the signals relative to MCLK is not generally specified for these interface devices as there can only be one bus master, so it is not generally necessary to know the relationship to MCLK. If the processor is acting as a master on a different bus then using the same MCLK should keep things synchronous. While we don't have specs for this, I wouldn't expect the delay between MCLK and other clock edges to be much more than 15ns or so.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    Genius 3885 points

    Hi Zak,

    Thank you for your prompt reply.

     

    We have informed it to the customer and waiting their feedback.

     

    Regards,

    Mochizuki