PCM1865: PCM1865 4CH I2S

Hi, Zak,

Many Thanks!

Further more, if comparing with low noise opa2350 , could the PGA inside the ADC outperform  the former in the noise figure?  I was considering the gain distribution between the front OPA and the inside PGA and could you please give some advice?

IBest Regards,

James

Hi, Zak,

Many Thanks! Great help!

Further testing show that there have a a little higher leakage of the fs/4 component in the output , regardless of the fs either 96k or 192k . The leakage is about 5-10db above the output noise floor and will disappear if running at fs 48k. The ADC is powered by the the LDO +3.3v, and the system is powered by a bulk mode DC-DC converter +5v , which is synchronized to 384k ,twice of the max fs  192k.  Where might the fs/4 signal come from? could you please give some advice ?

IBest Regards,

James

Hi James,

I'm not sure why you would see increased leakage at fs/4. Do you have any data you can share?

Best,

Zak

Hi, Zak,

Many Thanks! 

We are running the adc in a sampling detector with the full signal bandwidth of fs/2. When no signal input, the adc should output the flat backgroud noise floor after the FFT. There have some peak signal at the fs/4 when fs=96k or 192k.  The level will be 5-10db higher than the floor. But when fs=48k, the backgroud  is much clean than above. The peak signal seem some kind of leakage inside the adc, and outside the 20khz audio bandwidth. Any possible reason, could you please give me some advice ?

Best Regards,

James

Hi, Zak,

Further information. 

The PGA have been set to the maximum 32db without signal input. The 3.3v VDD is from a dc-dc converter which was synchronized to 384KHz. Do you think the fs/4 component is coming from the intermodulation interference of the spike from the dc-dc converter?  But why is the fs/4?

Would like to have your advice.

Best Regards,

James

Hi, Zak,

Please refer to the attahced. This is the FFT result of the ADC data. The full span is Fs= 192k and the 2 spike near the center is the +-Fs/4 leakage signal, with the level +13db higher than the noise floor. If change Fs to 96k, the spike is still the same position, but just 7db higher than the noise floor.

I am running the adc in 4CH mode and left the other 2CH input float. There have not such Fs/4 clock on my board and the Lowest clock is the LRCK ,192K, and the BCK is 6.144Mhz. So I can not image where is the leakage coming from.  Inside or outside the chip?

Whould like to have your further advice!

Best Regards,

James

Hi James,

Thank you for sharing more system details. I'm not sure exactly where this tone is coming from. I would recommend trying a couple things:

1) If you can, change the switching frequency of your DC/DC converter, or drive the PCM186x from an LDO or a battery to see if the behavior of the tone changes.

2) Measure with lower PGA gain to determine if this is arising from the front end or in the modulator. If it changes with PGA gain this may be an idle tone, and I will try to verify this on my end.

Best,

Zak

Hi, Zak,

Many Thanks!

Test report:

1. There is no obvious change when changing the frequency of DC-DC converter or  adding the LDO. 

2. Also to the PGA setting, no obvious change  even in the 0db. 

3. Disconnnect the input of ADC to the front end amplifier , the Fs/4 tone became weaker, but still noticable. 

Further information. 

The ADC is running in master mode with a 24Mhz clk and the PLL is locked on 98.304Mhz.

Would like to have your further advice.

Best Regards,

James

Hi James,

I apologize for the delay as I was out of office for the past week. I am going to see if I can recreate this behavior on our EVM, but due to conditions in Dallas from the recent snow storm I will not be able to get into the lab until next week. Please let us know if you have found any resolution on your end!

Best,

Zak

Hi, Zak,

Many Thanks for your kindly reply!

No progress now. We doubt the leackage must have some relationship with the Fs.  There have 6 kind of fixed clock source in my broad, 24Mhz , 25Mhz, 98.304Mhz, 6.144Mhz, 96Khz and 384Khz. Considering the leackage were around +10db above the noise floor and so weak, which clock could be the main reason?

Best Regards,

James

Hi, Zak,

Many Thanks for your so detail information!

It seems the leakage is coming from the ground noise coupling  from the MCU.  The strong common mode  noise might leak into the L and R channel preamplifier  before the ADC through the power rail.  I am using the single end input mode for ADC and how about the diffirential mode for the common noise suppression?  

Best Regards,

James

Hi, Zak,

Many Thanks!

I will try to modify the hardware!  Great help!

Best Regards,

James