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PCM1862: Remaining Fade-in status

Part Number: PCM1862

Hello Expert,

I have question regarding PCM1862's register status.

I supplied I2S signal to PCM1862 under slave mode then device output expected data signal. Moreover we can control gain and some EQ register.
However, page:0 register 0x72's status is 0x04(Fade in).

My understanding for Fade in is only asserted when output is ramping up.
However, our observed result is 0x72 register maintain Fade in status even if audio data ramped up.

For above situation, would you answer following questions?
1. Is this behavior expected?
2. Would you tell me the criteria of asserting fade in status?
3. Is there any work around for this phenomena?

I'm looking forward to hearing back from you.

Best regards,
Kazuki Kuramochi

  • Hi Kuramochi-san,

    It's good to hear that you are not having any control issues with the PCM1862.  The only other state I can think register 114 might take under normal operating conditins would be 'Run'.  If you go into standby or sleep mode and come back to normal operation, is the readout still Fade In or is it Run?

  • Hi Tom-san,

    I confirmed status register under the condition that will cause sleep as follows.

    1. Stop not only audio signal(it is same as zero audio data) but also BCLK and LRCK.
    2. Confirmed 114 register.

    I expect this procedure will lead sleep mode but mode register still in Fade in.
    Also, I confirmed register after start up when we followed p81's recommended Power on sequence.
    However, register is still Fade-in.

    Would you provide following points to us?

    1. expected root cause
    2. work around

    I'm waiting your feedback.

    Best regards,
    Kazuki Kuramochi

  • Hi Kuramochi-san,

    The status register should only read fade-in on startup. This can also potentially happen though if clock cycles are being missed, possibly due to a faulty ground connection and the device is repeatedly entering the fade-in state. 

    Are you certain the output data is fully ramped up? Are you able to measure close to a 0dBFS (4.2Vrms differentially) signal consistently? 

    Stopping the clocks should cause the device to enter the 'wait clock stable' state, which is not the same as putting the device in sleep mode. 



  • Hi Tom-san, Zak-san,

    I'd like to continue this discussion by mail.

    Thank you and best regards,
    Kazuki Kuramochi