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TLV320AIC3104 minimum register configuration

Saurabh Patel
Intellectual 590 points
Other Parts Discussed in Thread: TLV320AIC3104

Hi 

I need information for Minimal register configuration for TLV320AIC3104 playback.

AIC3104 is configured in master mode.

Is it possible to use AIC3104 without MCLK?

  • 0
    TI__Guru* 84915 points

    Hi, Saurabh,

    Please take a look at the following script.

    Playback_Master_Mode.txt 
    # BCLK = 1.536MHz; WCLK = 48kHz
# MCLK = 24.576MHz
#
# Page 0
w 30 00 00
#
# Software reset
w 30 01 80
#
# PLL Programming (Q = 4)
w 30 03 20
#
# Clock Register
w 30 65 01
#
# Master mode
w 30 08 c0
#
# Codec Data-Path Setup
w 30 07 8A
#
# DAC Power and Output Power Control
w 30 25 C0
#
# DAC Output Switching Control
w 30 29 02
#
# Left-DAC Digital Volume Control
w 30 2B 00
#
# DAC_L1 to LEFT_LOP/M
w 30 52 80
#
# DAC_R1 to RIGHT_LOP/M
w 30 5C 80
#
# LEFT_LOP/M Output Level
w 30 56 09
#
# RIGHT_LOP/M Output Level
w 30 5D 09

    The TLV320AIC3104 BCLK and WCLK will be configured as outputs in master mode. So, it is necessary the usage of the MCLK.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 590 points
    Hi Luis

    Thank for the script.

    After this setting I have seen more distortion in the signal.

    For 48KHz playback.

    # Codec Data-Path Setup
    w 30 07 8A

    Should be

    w 30 07 0A

    Please correct my understanding is wrong.
    Please confirm that provided script is for 48KHz playback.

    Thanks
    Saurabh
  • 0 in reply to Saurabh Patel
    TI__Guru* 84915 points
    Hi, Saurabh,

    You're right. The command line must be w 30 07 0A. The rest of the configuration must work for 48kHz with a MCLK = 24.576MHz. Could you provide plots of your output signal and a schematic if possible?

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 590 points
    Hello Luis

    Distortion is removed with
    43: Left-DAC value set to 0x30
    44: Right-DAC value set to 0x30

    At this stage I cannot share the schematic due to NDA.

    Do you think there will be HW filter issue or Any SW gain control is remaining?

    Thanks
    Saurabh
  • 0 in reply to Saurabh Patel
    TI__Guru* 84915 points

    Hello, Saurabh,

    The distortion problems are often related with the clocking configuration. However, the register configuration related with the sampling rate is correct.

    Also, this kind of problems is related with power supply sequencing and ground planes. The analog activity must be separated from the digital activity. So, we suggest to separate the analog ground plane from the digital ground plane and join them in one point. Also, could you provide information about the power supply sequencing? See 12 Power Supply Recommendations section for details.

    Best regards,
    Luis Fernando Rodríguez S.