I would like to use the TAS5760M chip in a noise cancellation application where extremely low delay is critical. Can you please provide an estimate what level of delay from I2S sample bits entry to setting the voltage on the speaker terminals is to be counted with ?
Looking at the chip architecture I am worried some delay may be introduced in particular by:
- I2S port (low risk here),
- all digital processing - HPF filter, interpolation filter and possibly digital cliipping - here the delays can be quite significant, depending on the implementation.
Regards, Pawel
