TLV320AIC3204: The delay time between digital audio input and analog audio output of Audio DAC

Wells, 

the latency from the filters is the primary source for delay.  This is described in the Applications reference guide.  For Interpolation filter A (44.1/48k) the delay is 21/Fs.  

which should not be anywhere near the kind of delay you are seeing. 

One possible explanation for this is that you are using the PLL, and you are not providing clocks until the Audio plays.  Thus the PLL needs to Lock, And then there is the delay of the filter added on top of that.  

another possibility or contributing factor is that the softstepping is enabled, the soft stepping ramps the audio volume up to avoid clicks/pops when unmuted.  

any additional details you can provide would be helpful

best regards,

-Steve wilson

Wells, 

I was just thinking,  one easy way to test what is happening, would be to provide a signal that has a controlled variation.  for example a sine wave that steps in frequency or amplitude. it is very likely that when you do this you will see that the delay is far less, and that there is simply a delay in turning on the output block. 

best regards,

-Steve wilson

Hi Steve,

I am so sorry for the delay reply. These day, we were trying all methods to decrease the latency.

Our test results are below:

If the MCLK is provided all the time and the CODEC is active all the time, the latency between 

receiving I2S signal and outputting analog audio signal is minimum.

The latency is about 2.88ms.

But the power consumption is bigger if the CODEC is always active.

The current of CODEC are 6.4mA @active, and 70uA @ idle.

We require the CODEC small latency time and low power consumption. If there is no voice to be 

played, the CODEC should be idle. If the is voice to be played, the CODEC should immediately 

output the voice in several milliseconds. What should we do? Please help us. Thank you!

Best Regards,

Wells

Wells, 

are you putting the codec in hardware reset when it is not active? 

What is your MCLK?  are you using a resource heavy processing block? 

You could try using the clock dividers only, and not the PLL,  then power down the analog blocks, but keep the Digital portions running.  

best regards,

-Steve Wilson

Hi Steve,

(1) We only put the CODEC in hardware reset when the whole board and CODEC are power on.

When there is no Audio to be played, the CODEC is still powered, and will not be in hardware reset.

And some registers of CODEC, such as bclk_n, madc、nadc、mdac、ndac、pll and master clock will be switch off. 

Please refer to the below picture.

(2) Regarding MCLK, we tried two methods: using PLL or not.

     a. Using PLL: An A5 MCU will send 3MHz clock to CODEC as MCLK.  The CODEC register is set as below.

       b. PLL is not used: An A5 MCU will send 12MHz clock to CODEC as MCLK.  The CODEC register is set as below.

           We found that there was some noise when voice was played if 12MHz clock was used.

           If 24MHz clock is used, nothing can be heard when the voice was played.

(3) Can you provide the actual delay time of this CODEC?

(4) If TLV320AIC3204 can't meet our requirement, can you advise other CODEC solutions to us?

Best Regards,

Wells

Wells, 

I've mentioned before that the Group delay of the interpolation filter is 21/Fs.  in the case of Fs= 8k  this is approximately 2.625msec.  Which aligns with what you are seeing. The Group delay of the interpolation filter is going to make up the overwhelming majority of the delay. 

The 21/Fs delay is pretty standard for codecs in our portfolio there are some as low as 17/Fs. One way to reduce the delay considerably would be to increase Fs.  

best regards,

-Steve Wilson

Hi Steve,

As I said, we want to use this CODEC in a two-way radio product. For the two-way radio, timing delay from the sender making a call and the receiver hearing a voice is limited. So we should decrease the CODEC delay from receiving I2S signals and outputting analog audio signals.

Our requirements are below: When there is no voice to be played, the CODEC is in a low power mode. Meanwhile MCLK will not be provided. When there is a voice to be played, the CODEC should be changed to be in active mode quickly and MCLK is provided immediately.

Regarding 21/Fs Group delay, we had tested this data. It's okay. But in order to get this minimum delay, the CODEC should be kept active and MCLK should be provided all the time. The consumption is high. The current of CODEC in active mode is about 6.4 mA@3.3V. 

But for TLV320AIC3204, I2C communication is required to wake up the  CODEC. The delay of I2C  communication is about 40~60ms.

How can we solve this problem? If TLV320AIC3204 can't meet our requirements, can you advise another solution for us? Thank you!

Best Regards,

Wells

Wells, 

I would suggest taking a look at the application report for Sleep/Standby modes for this device 

I noticed this there:

This may help reduce the time.  

Also It looks like your DAC over sampling rate is set to 768 for all of the PLL configurations. Assuming we can get your power up time reduce to an acceptable place, We should address this.  we can drop the DOSR to 128 or even 64 to help reduce power when active. 

Also if your processor can provide a 24.576MHz MCLK, that would allow us to eliminate the use of the PLL,  which would reduce current draw as well. 

best regards,

-Steve Wilson