TLV320AIC3104: Is there a max rising/falling time requirement for BCLK for TLV320AIC3104?

Ted Zhang

Part Number: TLV320AIC3104

Hi,

My customer is having some EMC issue and found that the root cause for the emission is the BCLK. They try to slower down the rising/falling time of the BCLK and pass the EMC requirement. However in our datasheet there is requirement for the maximum rising/falling time especially when device configured as slave mode(only 4/8 ns as below picture), why so rigid requirement here for the rising/falling time and if any risk when exceeding the required timing?

over 4 years ago

0 Ted Zhang over 4 years ago

TI__Intellectual 2280 points

HI team,

There is also a requirement that the delay time AVDD to DVDD can not exceed 5ms, it is also a very rigid limit. Is it necessary too? And if any risk to exceed 5ms?

0 Ted Zhang over 4 years ago

TI__Intellectual 2280 points

HI team,

There is also a requirement that the delay time AVDD to DVDD can not exceed 5ms, it is also a very rigid limit. Is it necessary too? And if any risk to exceed 5ms?

0 Ted Zhang over 4 years ago

TI__Intellectual 2280 points

HI team,

There is also a requirement that the delay time AVDD to DVDD can not exceed 5ms, it is also a very rigid limit. Is it necessary too? And if any risk to exceed 5ms?

0 Diljith over 4 years ago in reply to Ted Zhang

TI__Expert 6440 points

Hi Ted,

Our device expert is away for Christmas break and is expected back first week of January. We will respond back to you when he is back.

Best Regards.

0 Aaron Estrada over 4 years ago in reply to Diljith

TI__Mastermind 22950 points

Hi Ted,

Let me check with the design team on this. I will get back to you as soon as possible.

Regards,

Aaron

0 Ted Zhang over 4 years ago in reply to Aaron Estrada

TI__Intellectual 2280 points

Hi Aaron,

Could you please let me know if any feedback?

Thanks

0 Aaron Estrada over 4 years ago in reply to Ted Zhang

TI__Mastermind 22950 points

Hi Ted,

Apologies for the delayed response.

Relaxed rise/fall times on BCLK/MCLK/FSYNC will lead so a somewhat higher IOVDD current but should still be less than mA so may not be a concern. If the relaxed rise/fall times are used as input to PLL, jitter can be introduced and in turn can expect some slight performance degradation.

The power supply sequencing is a recommended sequencing for the most robust operation. The codec is extremely tolerant as it is but there is a chance some unexpected behavior may occur if the sequencing is not followed.

Regards,

Aaron

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TLV320AIC3104: Is there a max rising/falling time requirement for BCLK for TLV320AIC3104?