• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 290 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCM1794: About lowing down output distortion

louie li
Prodigy 170 points
Part Number: PCM1794

Hello TI engineer,

I am now designing a Audio Decode with PCM1794. Absolutely lowing distortion Is the most important thing in designing.

Firstly, I understand that perfect power supply Is important and so Is impendence parity and layout shelding.

The question comes from System clock, meanly MCLK supplied to DAC. Is it true that as long as the MCLK Is perfect enough and jitter of I2Ss are not large enough to induce data mistake, The analog output will be idealy perfect?

For example, if the mclk Is 24Mhz, jitter of I2S Is several periods of the MCLK, Can DAC correct such jitter from LRCK SCLK and Data route of I2S?

That would be a great help If there are relative documents as well as lines of answers #^_^#

Best wishes,

Louie LI

  • 0
    TI__Guru 52753 points

    Hi Louie, 

    The most important thing to avoid is synchronization error.  This begins with a low-jitter MCLK.  If you are creating all other digital signals from that same low-jitter MCLK signal, you are doing the correct thing.  You can also add some simple flip-flop gates to re-synchronize the other I2S signals to the MCLK if you would like, but generally jitter on the LRCK, BCK, and DATA do not impact performance unless the jitter of those signals is wider than 1 MCLK period.

    Thanks,

    Paul