DRV602: DRV602 Failed with 5V PVDD But Passed with 3.3V PVDD

Hi, Wayne,

The 3V level at the EN pin seems to be near of the marginal value for VDD = 5V. Could you test increasing this EN pin level and see how it results?

Best regards,
Luis Fernando Rodríguez S.

Thank you for your advise, Luis. The failure DRV602 is malfunction with 5V EN. It works with 3.3V PVDD and 3.3V EN. Should we submit this part for FA?...Wayne Chen 

Hi, Wayne,

Excuse me, could you clarify this issue? In your first post you mentioned that the enable signal was fixed at 3V and it works at PVDD = 3.3V but it doesn't work for PVDD = 5V. Does EN pin have a different voltage level at PVDD = 5V?

Thank you.

Best regards,
Luis Fernando Rodríguez S.

Luis,

Sorry for my inprecise statement. The EN was fixed at 3.3V. The failure DRV602 works with 3.3V PVDD + 3.3V EN, but malfunction with 5V PVDD + 5V & 3.3V EN.
Customer's target design is 5V PVDD + 3.3V EN. 

Thank you and Best regards,

Wayne Chen
06/23/2020 

Hi, Wayne,

Sorry, for some reason I didn't receive the notification from your response and I have missed this e2e thread for days.

Do you have new observations on this? Was the customer able to find a solution?

Best regards,
Luis Fernando Rodríguez S.

Hi Luis,

Customer returned a failure device to me. I will test it on the EVM and will keep you updated of my test result.
We will submit it to QA team if I got the same result as customer.

Thank you and Best regards,

Wayne Chen
07/22/2020

Hi Luis,

We can reproduce customer's problem with 5.2V VDD and 3.3V Enable signal on the DRV602 EVM.
Here are my process:





1. Removed LDO and reset IC from the EVM. Sent 5V VDD and 3.3V EN externally.
2. Check DRV602 output by Audio Precision equipment. 



1. Apply 5.2V VDD and 3.3V EN simultaneously -> No output from DRV602 device
2. Apply 5.2V VDD, then assert 3.3V EN to high -> DRV602 works normally.
3. Apply 5.2V VDD and 5.2V EN simultaneously -> DRV602 works normally.
4. Apply 3.3V VDD and 3.3V EN simultaneously -> DRV602 works normally.

Would you please advise the power sequence specification of the DRV602 device? We see a suggestion on the DRV602 datasheet but detail timing is not provided.



Power Sequence Test Result:

CH1=3.3V EN, CH4 = 5.2V VDD, CH2=VIN, CH3=VOUT

5.2V VDD -> 25ms -> 3.3V EN -> Failed




5.2V VDD -> 1 second -> 3.3V EN -> Failed



5.2V VDD -> 2.5 second -> 3.3V EN -> Passed



Thank you and Best regards,

Wayne Chen
08/10/2020
  

Hi, Wayne,

Could you also monitor the input AC-coupling capacitors level? As mentioned in the datasheet, they should be fully charged before asserting the EN pin.

Best regards,
Luis Fernando Rodríguez S.

Hello Luis,

Can DRV602 consist malfunction by asserting the EN to high before fully charged? We need to power cycling the device to bring it up again.

Thank you and Best regards,

Wayne Chen
08/12/2020

Hi, Wayne,

Yes, since the EN pin level is near of the 60% of VDD, it is important to wait until all the capacitors and VDD level is completely stable. Otherwise, the device will fall in a failure state.

Best regards,
Luis Fernando Rodríguez S.

Hello Luis,

Thanks a lot. Would you please teach us how to calculate charge time to ensure the quality of design?
We saw failure with 4 second delay between stable VDD and enable signal.

Thanks a lot,

Wayne Chen
08/18/2020

Hello Luis,

The issue can be solved by reducing VDD from 5.18V to 5.14V. Would you pls provide tips to explain the issue?

Thank you and Best regards,

Wayne Chen
08/19/2020

Hello, Wayne,

I have some questions regarding the VDD and EN pin voltage measurements. Do the voltage measurements are taken directly on the VDD and EN pins and referenced directly to the pins 5 or 10? Since the voltage levels you mentioned respect the conditions of the datasheet, we are thinking that the levels on the pins are not being taken correctly. The EN pin high-level input voltage level is above 60%, so there shouldn't be issues. Could you double confirm?

Best regards,
Luis Fernando Rodríguez S.