Part Number: TPA3144D2
Please let me know about three points below for TPA3144D2 maximum rating.
①Datasheet page 5 is not described maximum rating of GVDD (Blank).
Is there test data for GVDD maximum rating?
Or, I guess that GVDD rating is 20V because GVDD pin is nearly AVCC LDO by datasheet Page 12 circuit, is it correct?
②What is "minimum load resistance: RL" mean?
Is RL rating depend on maximum output power or current?
If there any other factor, please let me know.
③Is there the other spec for internal FET?
Is FET important point only PVDD and thermal loss?
Any update on this?
Additional question is below;
④A few pins maximum rating are restricted slew rate no more than 10V/ms or 100V/ms, and higher slew rate should to connect 100kΩ.
Is there any limiting condition or operating risk from connect 100kΩ?
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In reply to Satoshi:
Please see my comments.
1) GVDD is the internal regulator output, not power supply input. GVDD is usually 7V. You do not need take care of it.
2) minimum load resistance: RL is related to the OC threshold.
3) The Rds(on) of FET is in datasheet(Page 6), it is related to efficiency and thermal.
4) higher slew rate may have risk for internal ESD protection, so suggest to connect 100K resistor for higher slew rate power.
In reply to Yanming Gong:
Thank you for reply,
Sorry for additional question about ②.
What is the accuracy of RL rating (or OC threshold)?
TPA3144 OC threshold is 3.5A.
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