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PCM1863: PCM1863 Secondary ADC. Operation and ADC value conversion

Part Number: PCM1863

This is a follow up question related to the following issue

https://e2e.ti.com/support/audio/f/6/t/849586?tisearch=e2e-sitesearch&keymatch=secondary%20ADC

The instruction on reading and interpreting the secondary ADC is very limited. Is there newer datasheet or application note available? 

We are using one of the VIN pin to read the DC value. We see the 16-bit value in the AUXADC registers and also the 8-bit DC LEVEL register. However, we have a hard time to translate that value into Voltage level. 

Kimpik

  • Hi Kimpik,

    I apologize for the delay in responding, unfortunately we do not have any additional documentation on the secondary ADC. Since there isn't a defined transfer function, I measured some data in the lab to derive one empirically. I have attached my spreadsheet with my calculations. For the converter I measured, the input voltage can be approximated as ADC Input Voltage = (Decimal Output / 65536) * Full-scale range + 1.804V, where the full scale range I measured was 5.17V and the output corresponding to 0 code is 1.804V. I would expect this to vary a bit between devices since  the full scale may change slightly as well as the 0 code level, but you can use this as an approximation. Since the secondary ADC only has 12 bit accuracy, I would not expect the difference in gain error between devices to be too significant, but if you need better accuracy you could always follow a similar approach to what I have done to characterize the secondary ADC.

    Note this is for the 16-bit register. If you are using the 8-bit register then this data is stored in binary format, not 2's complement. The datasheet mentions a maximum input voltage of 4.3V is supported, so you can approximate the value as Input Voltage = (Code/255)*4.3V.

    PCM186x Secondary ADC Transfer.xlsx

    I hope this helps!

    Best,

    Zak

  • Thanks Zak, 

    thanks for your time. 

    Was the LPF coefficient registers updated while the data was collected? 

    Is there any HW guideline on the analog inputs? 

    The value read from AUXADC registers does not seem to change linearly according to the input voltage changes, 

    And it certainly fails to recognize small voltage changes in the 100mV range. 

    - kimpik

  • Hi Kimpik,

    I'm not sure I understand. I did not adjust the LPF coefficient registers but I was measuring dc voltages so this would have no impact (assuming you wait long enough for the converter to settle but this happens very quickly). All of our layout recommendations are given in section 12 of the datasheet and there isn't anything special that needs to be done for the inputs. 

    How are you reading the AUXADC values? In my measurements the data was very linear. You do have to write the AUXADC_LATCH bit to initiate a read and keep in mind the output is in 2'complement. The secondary ADC has a resolution of 12-bits so it can easily detect changes as small as ~1mV so I suspect there is an issue in how you are reading the data from the secondary ADC.

  • Thanks Zak, 

    We were also measuring DC voltage so we were surprised to see the AUXADC value changes given different coefficients used in the LPF registers. 

    Here are the AUXADC value 

    Volt AUXADC
    0 0xA986
    0.1 0xC0DB
    1.65 0xFA9E
    3.3 0x4C04
    4.8 0x7FFF

    Here are the register values written before reading the AUXADC 

    write_u8(0x00, 0x00); // switch to page 0
    write_u8(0x0A, 0x05); // SEC_ADC_INPUT_SELECT CH3L
    write_u8(0x58, 0x80); //
    write_u8(0x58, 0x90); // Toggle 0x10

    rd[1] = read_u8(0x58);
    rd[2] = read_u8(0x59);
    rd[3] = read_u8(0x5A);

  • Hey Kimpik,

    The sequence of your register writes and reads look correct, but when you write register 0x58 if you want to read DC values you should set the DC channel in the last 3 bits of this register as well. For you you would want to write 0x84 to read CH3L and then toggle the AUXADC LATCH bit after the data ready bits are flagged. So I would write 0x84 to register 0x58, add a short delay, then read 0x58 to confirm the data is ready to be read and then write the auxadc latch bit.

    Best,

    Zak

  • Thanks Zak, 

    Just to clarify the proper sequence for reading a DC value. 

    write_u8(0x00, 0x00); // switch to page 0

    write_u8(0x30, 0x10);  // set CH3L to DC level-change detection

    write_u8(0x0A, 0x05); // SEC_ADC_INPUT_SELECT CH3L

    write_u8(0x58, 0x84); //

    *Add Delay 

    buf = read_u8(0x58) 

    *Check bit 5 of the 0x58 register for DC_RDY bit?  Is this the right bit to check if DC value is ready?


    write_u8(0x58, 0x94); // Toggle AUXADC_LATCH bit

    buf = read_u8(0x4E);  // Read SIGDET_DC_LEVEL_CH3_L

    With our experiment, the DC_RDY bit was ever set. 

    Thanks.

  • Hey Kimpik,

    This seems to differ from your initial sequence. Also sorry for the confusion, but there are two different paths for reading the DC voltages, either in controlsense mode or through the AUXADC latch registers.

    If you are only using the AUXADC registers then your sequence could look like this:

    write_u8(0x00, 0x00); // switch to page 0

    write_u8(0x0A, 0x05); // SEC_ADC_INPUT_SELECT CH3L

    write_u8(0x58, 0x04); // Set AUXADC to read DC of CH3L (note it's not necessary to have the latch operation bit because that applies to the SIGDET registers, AUXADC register reads are always latched)

    write_u8(0x58, 0x14) // Latch the DC data on CH3L

    read_u8(0x58) // verify the AUXADC_RDY bit is set high, if it is then proceed

    read_u8(0x59) //Read AUXADC data

    read_u8(0x5A)

    write_u8(0x58,0x04) //Reset the latch bit

    Note in this case it's the AUXADC bit and data you care about, not the DC_RDY bit.

    Best,

    Zak

  • Zak, 

    thank you for your detailed response. 

    would you please advise on how to read the DC value in Controlsense mode? 

    We are not able to get a reasonable value from the AUXADC with the instruction suggested. 

    We want to explore the possibility of reading the value in ControlSense mode.

    Thanks again for your time

    Frances 

  • Hi Frances,

    The original sequence you posted should work and you can remove the writes to the latch bit:

    write_u8(0x00, 0x00); // switch to page 0

    write_u8(0x30, 0x10);  // set CH3L to DC level-change detection

    write_u8(0x0A, 0x05); // SEC_ADC_INPUT_SELECT CH3L

    write_u8(0x58, 0x84); //

    buf = read_u8(0x4E);  // Read SIGDET_DC_LEVEL_CH3_L

    Best,

    Zak