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SRC4392: auto-detect/set varying SPDIF input sample rates possible?

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Replies: 7

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Part Number: SRC4392

Hi TI,

I'm working on a design which might use the SRC4392 as SPDIF receiver to SRC to I2S slave.

What I need is totally automatic SPDIF receiving and sample rate converting independent of SPDIF sampling rate.

Right now we use the CS8422, but I'd prefer to use the SRC4392 for other reasons (CDAT and UDAT buffers).

The Receiver PLL1 Configuration Registers make me think that this is not possible, because the PLL1 settings

need to be adjusted when SPDIF input sample rate changes.

Real life application would be:

SPDIF input: any sample rate between 44.1kHz and 192kHz

I2S output: 100kHz sample rate, with an MCLK of 25.6MHz

Is that possible with fixed PLL1 settings?

  • Okay, not sure if I got that right now, after having checked some more forum threads...

    The PLL1 config registers must be set, so that:

    (CLOCK x K) / P = 98.304MHz

    with "CLOCK" in my case would be MCLK.

    So only if MCLK changes, the PLL1 settings need to be adjusted.

    Which means I can control that, because it's on the system's side, not on the "unknown SPDIF input side".

    Am I right?

  • In reply to Christian Erle55:

    Hello Christian,

    MCLK can be used as the SRC reference clock and does not have to related to or synchronous to the input or output sampling rates. 

    Regards,

    Aaron

  • Christian Erle55

    Part Number: SRC4392

    Hi TI,

    I'm working on a design which might use the SRC4392 as SPDIF receiver to SRC to I2S slave.

    What I need is totally automatic SPDIF receiving and sample rate converting independent of SPDIF sampling rate.

    Real life application would be:

    SPDIF input: any sample rate between 44.1kHz and 192kHz

    I2S output: 100kHz sample rate, with an MCLK of 25.6MHz

    Is that possible with fixed PLL1 settings?

    I recently completed an ADC and DAC design which uses the SRC4392 for S/PDIF I/O and DAC-side SRC. It does what you want, except that the output sample rate is fixed at 192 kHz with a reference clock of 24.576 MHz.
    The S/PDIF input auto-detects the incoming sample rate and the SRC follows it appropriately, with no intervention required.
  • In reply to Andy Peters:

    Hello,

    thanks for your replies, that helps a lot.

    I understand that we need to change the DIR's PLL1 settings in case I change MCLK.

    In our case it will change between 25.6MHz, 12.8MHz, 24.576MHz and 12.288MHz.

    That will not be a problem, the system knows when that switch occurs and can set the PLL1 registers accordingly.

    Next question... :-)

    Is the DIR able to receive an SPDIF/AES3 input with 200kHz or 216kHz sampling rate (and of course 24bits & 2 channels) ?

    If yes, is there anything that needs to be done with the PLL1 registers?

    Right now the PLL1 clock is set to 192kHz x4 x4 x32 = 98.304 MHz, which somehow lets me think that 192kHz is the limit for oversampling reasons.

    There is nothing else given in the datasheet concerning this clock rate. Is it necessary - and possible - to use (for example for receiving 200kHz) 102.4MHz as PLL1 clock ?

    I hope 200kHz will be possible, I want to get rid of that other chip...

  • In reply to Christian Erle55:

    Please, I really need this info before I order the first prototype boards:

    Is a non-audio sampling rate of the AES3 / SPDIF input possible, especially 200kHz or 216kHz?

    Again, the PLL1 target clock of 98.304 MHz (a multiple of 48kHz)  let's me doubt that.

  • In reply to Christian Erle55:

    Hello Christian,

    Yes. The DIR PLL lock range is from 20kHz to 216kHz. Those rates are supported. 

    Regards,

    Aaron

  • In reply to Aaron Estrada51:

    Thanks a lot, that settles it then, prototype boards will be ordered!