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TLV320AIC3204: after blocking the HPL/HPR output from DC, the test should see a 3.3V peak-to-peak 1kHz signal, right?

user5707026
Genius 3145 points
Part Number: TLV320AIC3204

Dears

The main control CPU sends a signal to the DA part of the TLV320AIC3204 chip. This signal has a conversion rate of 48kHz, 16 or 24 bits, 0dBfs, 1kHz single frequency. In other words, for the DA of the TLV320AIC3204 chip, it is an AC full-amplitude signal with a frequency of 1kHz.
When the HPL/HPR output amplifier is set to 0dB (no amplification or reduction), after blocking the HPL/HPR output from DC, the test should see a 3.3V peak-to-peak 1kHz signal, right? (Because LDOIN is 3.3V).
But the problem is that after the output of HPL/HPR blocks DC, the test peak-to-peak full range is only about 1.5V (the oscilloscope test voltage has a small error), which is the same as the setting mode of HPL/HPR using AVpp power supply (voltage 1.8V).

Thanks

Elsa Duan