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WEBENCH® Tools/LMK04828BEVM: Clock Configuration

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Replies: 12

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Part Number: LMK04828BEVM

Tool/software: WEBENCH® Design Tools

LMK_Queries.docx

  • Hello Shivaprasad,

    1. You are not getting the correct output because divide of one is an odd divide, and you must enable duty cycle correction for odd divides. Set DCLKout0_MUX, DCLKout2_MUX, and DCLKout10_MUX = 0x01 (Divider+DCC+HS).

    2. How are you measuring the 100MHz output? Are you using a balun, or have you terminated the unused leg of the differential pair to 50Ω?

    Can you tell me what synchronization procedure you are following? Note that section 9.3.3.1 of the datasheet explains the process of using the fixed digital delay to achieve a known phase offset between the outputs.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    using 1 point i will follow and tell you result.

    I measured by adding 50ohm to the output in spectrum analyzer.

    I have one more dought : i'm not getting smooth pulse it is some distorted, you can see that 2 screenshot of spectrum analyzer.

    Thanks &Regarde

    Basavakiran

  • In reply to BASAVAKIRAN HIREMATH:

    Hello Basavakiran,

    To confirm, you are referring to the distortion in this image:

    Typically when I see this kind of distortion it has two common causes:

    1. The other leg of the differential pair is unterminated. If output is LVDS for example, LVDS termination is 100Ω differential; both legs of the differential pair must see 50Ω to GND or 100Ω differential for proper termination.
    2. The output is terminated improperly. The default termination for DCLKout0, for example, includes 240Ω to GND, which would disrupt standard LVDS behavior. LVDS termination is specified in datasheet section 10.4.2

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek Payne,

     after adding 50ohm to the differential another end, I got little bit Smooth Output Signal,

    thanks for helping to solve my problem. I have one more dought 

    I want to program LMK with the help of Xilinx KC705 FPGA, how to connect and how to program LMK

    Thanks & Regards,

    Basavakiran

     

  • In reply to BASAVAKIRAN HIREMATH:

    Hello Basavakiran,

    After confirming your desired settings in TICS Pro, you can use TICS Pro to export hex register values:

    You can store the hex register programming in FPGA memory or read it in from some other external device. The register programming interface is a SPI bus which supports bidirectional read/write, see Figure 1 in the datasheet for the timing diagram.

    For writing to the device, the SCK, CS*, and SDIO pins should be connected to FPGA SPI clock, chip select, and MOSI nets respectively. For reading from the device, you can either use a bidirectional transmitter on the MOSI net and switch to receive mode for SPI reads as the data bits are transmitted, or you can use 4-wire SPI mode by configuring one of the GPIO pins (PLL1_LD, PLL2_LD, CLKin_SEL0, CLKin_SEL1, or RESET pin) for SPI readback, and connecting the readback pin to the FPGA MISO line.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek Payme,

    I used KC705 Xilinx FPGA in that I taken from XADC pins, from that i got Vp-p as 5 Volts, bt from LMK Vp-p was 2.2 Volts

    so from which pins of FPGA have to use for connecting LMK.

    Thanks & Regerds,

    Basavakiran

  • In reply to BASAVAKIRAN HIREMATH:

    Hello Basavakiran,

    The LMK04828 I/O levels are 3.3V. While I don't have access to the schematics or EVM documentation (Xilinx requires login for this information), generally you have a few options for communicating with any FPGA:

    • Use a 3.3V I/O bank on the FPGA (Is I/O voltage control available on the bank or pins connected to the XADC pins?)
    • Use a 5V to 3.3V level shifter between the FPGA and the LMK04828
    • Use resistor dividers to reduce the 5V FPGA level to 3.3V, and use an open-drain transistor inverter to 5V + set LMK04828 readback GPIO output format to push-pull (inverted).

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek Payne,

    I got output clocks but those are not in SYNC and default it is taking as Divider value as 2(means External input clock is 100MHz then I'm getting output clock was 50MHz) but i want divider value should be 1(I/P clock 100MHz, O/P clock 100MHz).

    How should i program DCLKout10_MUX = 0x01 (Divider+DCC+HS) and SYNC Divier - selection.

    I you tell me register address and value, some solution for this dought.

    Thanks & Regards

    Basavakiran

  • In reply to BASAVAKIRAN HIREMATH:

    Hi Basavakiran,

    The value of the DCLKout10_DIV (0x128[4:0]) should be set to 0x01 to ensure the divider value is 1. DCLKout10_MUX = 0x01 is correct for this mode.

    You must follow the SYNC procedure outlined in the datasheet in order to align the outputs. Paraphrased, this looks like:

    1. For each output you need to synchronize, set DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. For example, if all output edges should be simultaneous, set DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL to the same values across all outputs. Also, ensure that DCLKoutX_DDLY_PD is cleared to 0 on all outputs you need to synchronize.
    2. In the SYNC/SYSREF page, set the SYNC_MODE mux to pin mode (0x1), the SYSREF_MUX to normal SYNC (0x0), and the SYSREF_CLKin0_MUX to source from SYSREF_MUX (0x0).
    3. Ensure SYNC_EN is set to 1.
    4. For each output you need to synchronize, clear SYNC_DISx to 0.
    5. Synchronize the dividers:
      1. By pin: Apply an external signal HIGH to the SYNC pin, then LOW after at least seven CLKin1 clock cycles.
      2. By software: Toggle the state of the SYNC_POL bit (0 -> 1 -> 0).
    6. Set all SYNC_DISx bits to 1.

    I have included a TICS Pro profile which accepts 100MHz on CLKin1 and should generate 100MHz on DCLKout0, SDCLKout1, DCLKout2, and DCLKout10.

    LMK04828 100MHz in, 100MHz out.tcs

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hi Derek Payne,


    I'm getting 40ps delay in between DCLKout0, DCLKout2, and DCLKout10. i Changed  DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL register value also but there is no changes in that delay, what should i do?

    can I do Same procedure for DAC038J84EVM? DAC Mode (LMFS=4211).

    Thanks & Regards

    Basavakiran