I need to mute one of the outputs for a short period of time, to reset some FPGA logic. (I want other outputs to keep running)
Is there a way to power down / mute output (lets say 6) without re-syncing and stopping other clocks?
I tried muting it by:
1) OUTCTL_6 Register; R41. -> write 0 to OUT_6_SEL[ 1:0]. This should disable the driver. After reset I am switching it back to 1 (AC-LVDS mode).
2) PWDN Register; R30. -> Write 1 to bit 4.
Both options seem to be able to disable the output, but the clock is not coming up properly (it looks unstable or its not coming up at all)
What seems to fix that clock -> Recalibrate LMK by toggling soft reset.
R12 bit 7
ADDR: 0x0C, val: 0x5D
ADDR: 0x0C, val: 0xDD
However, this forces other clocks to pause as well.
So, is there a way to mute / unmute only 1 output on the chip? Without pausing other clocks?
Thank you,
Anton
