CDCI6214: Output frequency configuration problems

Hi Dominic,

Most of the register programming appears to be correct. I think your frequency error is a result of the crystal driver not being properly tuned for your crystal. I am looping in a colleague with greater part-specific knowledge for CDCI6214 to answer your questions.

Regards,

Derek Payne

Hi Dominic,

Can you check if PLL is locked first? You can do this in Ticspro. Read back all registers then check the value of register LOCK_DET.

If it doesn't lock, do below

1. Click "RECAL" 2. see if this turns into green "locked". 3. Now measure the frequency again.

Let's first make sure that the PLL is locked before moving into the crystal load cap direction.

Regards,
Hao

Hi Hao,

The PLL is locked,but the output frequency is 2MHz lower than the set frequency，how to solve this problem?

Look forward to your reply，thanks!

Regards,

li

Hi Li,

Can you then try changing the internal load capacitance? In general the load capacitance shouldn't cause frequency variation of as much as 2MHz but just try it first. Reduce the load capacitance here and see if the frequency goes up. Also, what's your load capacitance on the board?

If this doesn't help then check the output termination and try measuring it with an Oscilloscope or another frequency counter. Always double check the lock status.

Regards,
Hao

Hi Hao,

Thank you for your reply！

I tried to change the internal capacitance to 3pf,but the the output frequency does not change,and no matter the load capacitance on the board is 3pf or 12pF the the output frequency does not change too.

The PLL is locked

Regards,

li

Hi Li,

Try starting with the fallback mode by floating pin REFSEL and EEPROMSEL.

If everything's working in fallback mode, try loading the default in Ticpsro (in the tool bar, default configurations)

Regards,

Hao

Hi Hao,

I try starting with the fallback mode by floating pin REFSEL and EEPROMSEL,but there are no outputs;

And in fallback mode I try loading the default in Tics pro,there are no outputs,too

Regards,

li

Hi Li,

Are you using XTAL or external reference clock? If you're using 25 MHz XTAL, then you should be able to use the fall back default configuration.

Regardless, can you enable Y0 and measure the clock frequency from Y0? Y0 is the buffered output of the reference clock. So if Y0 is not accurate, then it means that the problem is with the reference clock.

Regards,
Hao

Hi Hao,

In fallback mode I loading the default in Tics pro,the four outputs are 156.25MHz，but the PLL is not locked。

Will this have any effect, will it make the output unstable？

Hi Li,

Are you using a XTAL or external reference for clock input?

Regards,
Hao

Hi Hao,

Yes,I using a XTAL  for clock input.

However, the output of cdci6214 is the same regardless of the external 12PF load capacitor or no load capacitor for the XTAL.

Hi Li,

This can't be true. Are you using a frequency counter to accurately measure the frequency? Can you send me the Ticspro configuration you are using (In Ticspro, File -> Save)? Since you are using 25MHz XTAL, fall-back default should work for you.

Regards,
Hao

Hi Hao,

I measured the frequency with an oscilloscope，here is the Ticspro configuration:

Fall-back_156.25.tcs

Hi Li,

A few things:

1. According to the schematic, the fall back default should give your some valid outputs. Check again if PLL is locked after toggling the "recal" bit. If unlocked, enable Y0 and see if there's any clock output from Y0.

2. For the previous configuration where you saw 2 MHz frequency error, measure the frequency with a frequency counter. If the error is still there, send me that configuration file.

Regards,

Hao