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LMK04806: LMK04806 problems encountered during debugging

Part Number: LMK04806

Dear Expert

In the process of debugging LMK04806, we met two problems, we would like to ask the original factory to help solve them.The detailed description is as follows:

1.PLL output cannot be locked, and LD_STATUS(PLL2_DLD) status indicator is flashing.The quality of power supply and input clock meet the requirements. We suspect that the configuration file is wrong, so we hope the original factory can help to provide a configuration file. The relevant conditions are as follows

(1) Mode select PLL2, int VCO,0-delay;OSCin_freq is 160 m;No synchronization is required;The configuration interface is shown below. Please do not modify the ones circled in red. Anything else is OK.

(2) The clock output interface is as follows. Please do not modify the part circled in red. The rest is OK

2. There is also a problem that the value of register R0 is not consistent with the value of register R0 written. The details are as follows:

(1) After power on, STATUS_Holdover is used as readback of uwire by default

Read R0:0x4000019

(3) R0:0x00142800

Read R0:0x50A00

Write R1:0x162801

(6) Read r1:0xb140

Hope you can reply as soon as possible. Thanks a lot!

  • Hi Gabriel,

    in 0-delay mode, PLL2_N_CAL must be equal to PLL2_N. 

    For example, if PLL2_N is 80, then PLL2_N_CAL must also be 80.

  • Dear Noel

    Thanks for your reply!

    1. As shown in the following figure, the clock can output correctly and the PLL can be locked.However, since I need to output a clock with a minimum of 1M, I need to use the VCO Divider.Oddly, when I chose the VCO divider MUX as a VCO divider, the VCO could not be locked and the clock could not output.What's the reason?Are there any other constraints when I choose the VCO Divider?

  • Hi Gabriel,

    The VCO Divider Mux is located in the feedback path, if you use it, the input frequency to the N2 Prescaler will be smaller.

    Once again, you have to change PLL2_N_CAL accordingly to match PLL2_N.