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CDCE813-Q1: jitter cleaner for serializer

Gerald
Genius 9570 points
Part Number: CDCE813-Q1

Hi Team,

My customer have a concern.
Please see below:

"I want to use serializers of the type SN65LV1023 and SN65LV1224 to transmit signals in repeater mode (see diagram) at a clock frequency of 12.288Mhz. The problem is the accumulative jitter that is generated in each repeater.
My question is, Is CDCE813R02TPWRQ1 really efficient using the factory default configuration to eliminate or attenuate the jitter that is generated in the RCLK of each repeater?
I send you attached oscillogram of the parallel clock received in the first repeater and after eight repeaters"

Diagram


RCLK in first Receiver

RCLK in eight Receiver



I hope you can help.

Thank you so much.

Gerald Millar


  • 0
    TI__Genius 11935 points

    Hello Gerald,

    Utilizing the CDCE813R02 or associated CDCE813-Q1 Programmable 1-PLL Clock Synthesizer and Jitter Cleaner broadband jitter can be significantly reduced.

    According to your design, by utilizing a PLL per link at RCLK the jitter should be brought down significantly as broadband jitter is filtered out. This cannot be continued indefinitely as PLL noise will add with previous PLL noise therefore increasing jitter.

    If a single PLL does prove to add to this noise in a significant fashion, a dual PLL jitter cleaner could be utilized to further reduce jitter further. This again cannot be continued indefinitely as PLL noise will continue to add.

    Hopefully this helps!

  • 0 in reply to Aaron Black
    TI__Genius 9570 points

    Hi Aaron,

    I got feedback from my customer and he said:

    "Thanks for your answer. I think that from what you tell me, the proposed solution may help but it is not perfect to use many repeaters in series.
    I have also thought that another solution may be to generate a new clock in each repeater and synchronize the data with a CDC (Clock Domain Crossing) type circuit, but I have done some tests with circuits based on Flip Flops (like the ones in the attached diagram) and a lot of data is lost. Do you know of an effective method to do this function without losing information?"

    I will be looking for your response.

    Again thank you so much for your help.

    Gerald

  • 0 in reply to Gerald
    TI__Genius 11935 points

    Hey Gerald,

    I'll have to think about this a bit. Let me get back to you soon.

    Also, stated previously the proposed solution is not perfect as this is by nature but has this been tested yet? I am not sure if with the amount of repeater circuits, and ultimately PLLs, you would have to worry about PLL noise adding significantly to the jitter.

  • 0 in reply to Aaron Black
    TI__Genius 9570 points

    Hi Aaron,

    Thank you for helping us.
    I also received a response from my customer and he said:
    " I am waiting for a possible answer. Meanwhile I am going to do a test with the CDCE813R02 and observe its behavior and take the measurements that I can. Have a great day. Thanks"

    We will wait for your response.

    Regards,

    Gerald

  • 0 in reply to Gerald
    TI__Genius 11935 points

    Hello Gerald,

    If we understand what is trying to be done - we can produce a phase synchronized output to each PLL of the serializer circuit, this PLL device would then utilized Zero Delay Mode. Utilizing this setup this would mean additive jitter of only 2 clocking devices - reference clock devices and then the serializer PLL.

    Optional devices for the phase synchronized output device would be an LMK048xx device.

    Keep in mind there would be two approaches to align the flip-flop re-timed and serialized output:

    Option 1. Adjust the clock phase separately for every board

    Option 2. Adjust the serializer phase separately for every board

    We would recommend if a common clock is already being utilized to sync all PLLs of synchronizers, then utilizing 'Option 2' and define the FIFOs read on rising edge, shift on falling edge and skip any possible issues of the flip flop propagation across production, voltage and temperature 'PVT'.

    Hopefully this helps.