LMK5C33216EVM: Zero Delay Mode - Details required

Part Number: LMK5C33216EVM
Other Parts Discussed in Thread: LMK5C33216

Dear All,

we try to use the LMK5C33216EVM in Zero Delay Mode and shift the output by a defined delay using DPLLx_PH_OFFSET. In a first test scenario, I use a 10MHz clock on REF0 and generate a 10MHz output on OUT0 via APLL1.

My questions / comments are:

1. Where Do I get detailled information how to calculate and choose correct parameters for the ZDM-settings? Data sheet, EVM-Manual and Programming guide do not really help me. E.g. In section 9.3.8.1, the data sheet states that the ZDM has an influence on the VCO-calculation, but not how to handle this and if it is covered by TICS PRO.

2. How large are the minimum and the maximum achivable delay and how can I calculate it (I assume these numbers depend on the VCO frequency) ?

3. How can I access the DPLLx_PH_OFFSET registers? Only via the raw registers in the TICS PRO SW?

4. If I try to use the button 'RUN SCRIPT' in the DPLL1-window, the sofware returns a python error: 'sREF0_FREQ is not defined' (However, it is defined).

5. When will TicsPro support the ZDM feature?

6. I use a Si5338 as REF-IN. It fullfills all requirements accordiing to section 7.5, but I get a lof of RFX_MISSCLK_STATUS events. Even setting the limits to the maximum in the VALIDATION page does not improve the behaviour. On the other hand, even if I set the reference to 11MHz (instead of 10MHz) the situation does not get worse. So I had to disable the missing clock window detector. Can this cause the DPLL not to phase lock (LOPL_DPLL1 is set)?

Can you please advice?

Best Regards, Thorsten

  • Hello Thorsten,

    we try to use the LMK5C33216EVM in Zero Delay Mode and shift the output by a defined delay using DPLLx_PH_OFFSET. In a first test scenario, I use a 10MHz clock on REF0 and generate a 10MHz output on OUT0 via APLL1.

    This is doable.  You will need to use OUT0, OUT4, or OUT10 for your feedback clock at 10 MHz.

    1. Where Do I get detailled information how to calculate and choose correct parameters for the ZDM-settings? Data sheet, EVM-Manual and Programming guide do not really help me. E.g. In section 9.3.8.1, the data sheet states that the ZDM has an influence on the VCO-calculation, but not how to handle this and if it is covered by TICS PRO.

    For your 10 MHz case,

    • if you go to the output page you want for ZDM feedback, click OUT_X_Y_ZDM_EN = 1 in the lower right.  If using OUT0 for ZDM, then you must also pick which TDC to provide feedback to.
    • For your 10 MHz in and out case, on the Zero Delay group of User Controls select...
      • TDCx_ZDM_BYPASS_FB = 1 (Bypass FB DIV)
      • TDCx_ZDM_FB_PRE_BY = 1 (Bypass FB Prescaler)
      • TDCx_IN_SEL = 1 or 2 as required depending on your choice of output and TDC.
      • TDCx_IN_DRV_SEL = 5 (Bypass feedback divider)
    • On DPLLx page.  In top right click DPLLx_ZDM_EN = 1.
    • You can adjust using DPLLx_PH_OFFSET.  After changing press soft-reset button.  Try making adjustments in 100,000s.

    2. How large are the minimum and the maximum achivable delay and how can I calculate it (I assume these numbers depend on the VCO frequency) ?

    You will be able adjust to any point on the 10 MHz period.  I would need to do a calculation to determine the total range, but I don't think it really matters because it will all be modulo 100 ns.

    Are you wondering because you are considering using lower frequencies like ZDM with 1 PPS?

    3. How can I access the DPLLx_PH_OFFSET registers? Only via the raw registers in the TICS PRO SW?

    The DPLLx_PH_OFFSET is located on the DPLLx page (under DPLL in tree).  It is located towards the right below the horizontal line in the PHASE LOCK group.

    4. If I try to use the button 'RUN SCRIPT' in the DPLL1-window, the sofware returns a python error: 'sREF0_FREQ is not defined' (However, it is defined).

    Please do not use the RUN SCRIPT button in the DPLL1 window.  For calculation of DPLLx loop filter and configuration, use the RUN SCRIPT at the bottom of the Start Page.

    5. When will TicsPro support the ZDM feature?

    It is possible by end of this month.  Otherwise I expect by end of next.

    6. I use a Si5338 as REF-IN. It fullfills all requirements accordiing to section 7.5, but I get a lof of RFX_MISSCLK_STATUS events. Even setting the limits to the maximum in the VALIDATION page does not improve the behaviour. On the other hand, even if I set the reference to 11MHz (instead of 10MHz) the situation does not get worse. So I had to disable the missing clock window detector. Can this cause the DPLL not to phase lock (LOPL_DPLL1 is set)?

    Did you click the run script in step 7 at the bottom of the Start Page?  This would help to setup this properly.

    73,
    Timothy

  • Hi Timothy, thanks for your help. Pleae find my answers below.

    Hello Thorsten,

        Thorsten Sokoll said:
        we try to use the LMK5C33216EVM in Zero Delay Mode and shift the output by a defined delay using DPLLx_PH_OFFSET. In a first test scenario, I use a 10MHz clock on REF0 and generate a 10MHz output on OUT0 via APLL1.

    This is doable.  You will need to use OUT0, OUT4, or OUT10 for your feedback clock at 10 MHz.

        Thorsten Sokoll said:
        1. Where Do I get detailled information how to calculate and choose correct parameters for the ZDM-settings? Data sheet, EVM-Manual and Programming guide do not really help me. E.g. In section 9.3.8.1, the data sheet states that the ZDM has an influence on the VCO-calculation, but not how to handle this and if it is covered by TICS PRO.

    For your 10 MHz case,

        if you go to the output page you want for ZDM feedback, click OUT_X_Y_ZDM_EN = 1 in the lower right.  If using OUT0 for ZDM, then you must also pick which TDC to provide feedback to.
        For your 10 MHz in and out case, on the Zero Delay group of User Controls select...
            TDCx_ZDM_BYPASS_FB = 1 (Bypass FB DIV)
            TDCx_ZDM_FB_PRE_BY = 1 (Bypass FB Prescaler)
            TDCx_IN_SEL = 1 or 2 as required depending on your choice of output and TDC.
            TDCx_IN_DRV_SEL = 5 (Bypass feedback divider)
        On DPLLx page.  In top right click DPLLx_ZDM_EN = 1.
        You can adjust using DPLLx_PH_OFFSET.  After changing press soft-reset button.  Try making adjustments in 100,000s.
            
    TS: Just a short additional information: Actually we need synchronized input- & output clocks, the zero delay betweeen them is higly desired but not 100% neccessary.

    So, I set up APLL1 (f_VCO = 5 GHZ) and DPLL1 and ran through all steps of the start page. The APLL1 locks and both References are valid (as long as I omit the T_early-check). The DPLL1 shows me a LOPL_DPLL1 and LOFL_DPLL1, which cannot be removed by step 7 of the start page. I applied the adviced settings (with TDC = 1), but there is still no stable relationship between my input and output.

    Can this be caused by the LOPL & LOFL of DPLL1?

    Can I send you my register settings for debugging?

        Thorsten Sokoll said:
        2. How large are the minimum and the maximum achivable delay and how can I calculate it (I assume these numbers depend on the VCO frequency) ?

    You will be able adjust to any point on the 10 MHz period.  I would need to do a calculation to determine the total range, but I don't think it really matters because it will all be modulo 100 ns.

    Are you wondering because you are considering using lower frequencies like ZDM with 1 PPS?

    TS: Exactly, even though we would be happy with 100Hz, too. How large would be the maximum shift for such a 100Hz-Signal be?

        Thorsten Sokoll said:
        3. How can I access the DPLLx_PH_OFFSET registers? Only via the raw registers in the TICS PRO SW?      

    The DPLLx_PH_OFFSET is located on the DPLLx page (under DPLL in tree).  It is located towards the right below the horizontal line in the PHASE LOCK group.

    TS: Thanks!

        Thorsten Sokoll said:
        4. If I try to use the button 'RUN SCRIPT' in the DPLL1-window, the sofware returns a python error: 'sREF0_FREQ is not defined' (However, it is defined).

    Please do not use the RUN SCRIPT button in the DPLL1 window.  For calculation of DPLLx loop filter and configuration, use the RUN SCRIPT at the bottom of the Start Page.
    TS: OK!

        Thorsten Sokoll said:
        5. When will TicsPro support the ZDM feature?

    It is possible by end of this month.  Otherwise I expect by end of next.
    TS: OK!

        Thorsten Sokoll said:
        6. I use a Si5338 as REF-IN. It fullfills all requirements accordiing to section 7.5, but I get a lof of RFX_MISSCLK_STATUS events. Even setting the limits to the maximum in the VALIDATION page does not improve the behaviour. On the other hand, even if I set the reference to 11MHz (instead of 10MHz) the situation does not get worse. So I had to disable the missing clock window detector. Can this cause the DPLL not to phase lock (LOPL_DPLL1 is set)?

           Did you click the run script in step 7 at the bottom of the Start Page?  This would help to setup this properly.

    TS: Yes I clicked, but it does not help. And even stranger: I connected the 38.88MHz-XO-signal via 0Rs (over C70 and C71) and the onboard straight SMA-connector to REF0_IN0_P and start with the default settings + entering 38.88MHz/CMOS for REF0 in Step 2 and activate T_early-detector. The REF0_Valid Status and the REF0_MISSCLK_STATUS are both high. How can REF0_MISSCLK_STATUS be high (The XO checks itself) and how can the overal status be valid if clocks are missing?

    After changing the output frequency of CH0 and CH1 to 38.88MHZ & stepping through step 5-7, I would expect a synchronized output between the XO and OUT. However, the signals are not synchronized (is this assumption correct?). A look onto the status page tells why:  DPLL2 and APLL2 are out of lock. What am I doing wrong?

    Best regards and thanks in advance,
    Thorsten


    73,
    Timoth

  • Thorsten,

    Timothy is OoO today, apologies for the delay. While we wait, can you upload the latest .tcs file from your setup? (File -> Save, not the export hex registers). If we can load your configuration on our setup we can probably narrow down whatever is going on with the paradoxical REF0_VALID/REF0_MISSCLK_STATUS, as well as the DPLL ZDM config and locking issues.

    Regards,

    Derek Payne

  • Dear Derek,

    sorry for responding late, but I was testing a lot and made some progress:

    1. For Ref-Inputs of 10MHZ, 1MHz and 200kHz I was able to setup OUT0 and OUT4 (I had to remove L1 & L2 on the Eval-Board) in such a way that I can delay them independently. I think using the SoftReset more often helped me a lot.

      However, the REFX_MISSCLK-issue is still present: https://hidrive.ionos.com/lnk/YvilFSzP

      The used Validation settings are shown here: https://hidrive.ionos.com/lnk/1BCFF5sE

      and still: If I enable the T_early-stage, the clocks become invalid (even if I use the 38.88MHz-XO as an input).

      Please find here (https://hidrive.ionos.com/lnk/nrilFUvm) the requested tcs-file for the 10MHz-input & -output.
    2. Currently I am working on a 1kHz-input & -output, but I have so far no success. Can you adjust the attached file, so that it works with a 1kHz input and output with ZDM for OUT0 and OUT4?
    3. The documentation for starting SYSREF via a GPIO does not match with TICS PRO. So I used the continuous mode in the output stages.

    4. Can you provide us the code for calculating the loop filters?

    5. In our application the REF-input can change between 1kHz and 100MHz and we need to adjust the PLL-settings on the fly. Is it possible to provide the result from the frequency measurement during REF-validation via I2C or SPI? This would make an additional frequency counter obsolete.
      If this is not possible, do you think that the TOD-Counter can be used to determine the Ref-frequency?

     And finally: again thanks to you and Timothy for the great support.

     Best Regards,
    Thorsten

  • Hello Thorsten,

    However, the REFX_MISSCLK-issue is still present: https://hidrive.ionos.com/lnk/YvilFSzP

    Let me confirm the REFX_MISSCLK polarity.

    Currently I am working on a 1kHz-input & -output, but I have so far no success. Can you adjust the attached file, so that it works with a 1kHz input and output with ZDM for OUT0 and OUT4?

    Currently I am working on a 1kHz-input & -output, but I have so far no success. Can you adjust the attached file, so that it works with a 1kHz input and output with ZDM for OUT0 and OUT4?

    Sure... Note that for the 1 kHz output, you'll need to enable the SYSREF divider and run it in continuous mode.

    The documentation for starting SYSREF via a GPIO does not match with TICS PRO. So I used the continuous mode in the output stages.

    Thanks for noting about the documentation for the EVM needing update.  Note for GPIO sysref request, you simply need to use SYSREF_REQ_SW to request the SYSREF.

      - Were you needing SYSREF pulse capabilities for JESD204B?  Otherwise you will want to use continuous SYSREF for low frequency output.

    Can you provide us the code for calculating the loop filters?

    We do not have this available.  Looking at your next question, I think that input flexibility is driving this?

    The loop filters don't have be be calculated exact.  Also the critical parameter is the TDC rate.  So for example you could have a 1 kHz TDC filter, 1 MHz TDC filter, 10 MHz TDC filter, then divide down any given frequency to the nearest TDC.  Would this approach work?

    In our application the REF-input can change between 1kHz and 100MHz and we need to adjust the PLL-settings on the fly. Is it possible to provide the result from the frequency measurement during REF-validation via I2C or SPI? This would make an additional frequency counter obsolete.
    If this is not possible, do you think that the TOD-Counter can be used to determine the Ref-frequency?

    So I understand that a reference is applied to the LMK5C33216 in your product.  But you don't know what it is.... so you have a separate frequency counter to determine the frequency so you could then make the

    What is the granularity you need to determine the input frequency?  Maybe I mis-interpreted above and it's just 1 kHz or 100 MHz you need to deal with and identify?

    I'll respond to your other questions next.

    73,
    Timothy

  • Dear Timothy,

    Thank you for your detailed reply. Unfortunately, I haven’t made any progress today, so I cannot give you more details, but will try to explain you our application:

    There are mainly two scenarios:

    1. We have an input clock with a duty cycle between 40-60% and a frequency between 1kHz and 100MHz. The output of our system consists of two clocks, which feature the same frequency, but are delayed by two independent delays. For smaller frequency ranges, I would use a delay line, but this is not reasonable for 1kHz up to 100MHz.

      This scenario already works with the LMK5C33216EVM down to 200kHz, but not below

     

    1. The second scenario, I haven’t mentioned so far: We have no input signal and the frequency (again between 1kHz and 100MHz) of the output clocks is provided by software. The both outputs should have the same frequency and an adjustable & stable phase relationship.

      I tried this by letting APLL3 run in free mode and feed its output divided by 4, i.e. 614.4MHz  to DPLL1 and DPLL2. To ensure that the maximum TDC1 and TDC2 frequency do not exceed 11MHz, the DPLL1 & DDPLL2 R-dividers are set to 500. Finally, I activated the ZDM. So far I was able to generate on OUT0 and OUT 4 two signals which are exactly at the same frequency, i.e. the phase relationship is constant (even though not exactly 0, but 5ns). But changing the DPLL1_PH_OFFSET or DPLL1_PH_OFFSET, does not result in a change of the phase relationship. The reason is probably, that I haven’t set up the ZDM correctly and that the DPPLs do not lock. I uploaded the tcs-file, maybe you can take a look at this, too.

     

    Best regards,
    Thorsten

  • Hello Thorsten,

    I expect to be able to try this config on Monday.

    73,
    Timothy

  • Hello Thorsten, sorry for the delay... I can get to this update this week... are you still in need of the 1 kHz ZDM config?

  • Hi Timothy

    yes, I still need the 1kHz ZDM config for the first scenario and also a solution for the 2nd scenario.

    If you think, that we can speedup the process by setting up a teams meeting, please send me some suggestions. I am typically well availabe in the eveneing hours (i.e. 5:00PM - 9:00PM CET).

    Best regards, Thorsten

  • Hello Thorsten,

    Sorry for the delay, but I did create a config which uses DPLL2/APLL2 to lock a 1 MHz input to ZDM with a 1 MHz output on OUT0.  The reference to APLL2 is the XO.
      - I did the 1 MHz because it appeared I had some issue

      - I actually found a bug in the software when attempting to enable cascade from another APLL for XO and then calculating the DPLL loop filter.  I was going to provide APLL3 as a reference to APLL2 XO.  I know you asked about provided APLL3 as a reference to DPLL2.  But I don't think that is going to be as interesting.

    In this case I had a split the reference and was able to align the output with the split reference.  Performing soft-chip reset shows that the output deterministically aligns with this split reference.

    On my setup with cables lengths as they were, the DPLL2_PH_OFFSET = 750000.  For this config an adjustment of 100000 results in a delta of about 12.5 ns.  So this shows a resolution of 125 fs.  The maximum value of DPLL2_PH_OFFSET = (2**45)-1 = 35184372088831

    So you won't be at a loss for tuning the full range of a clock.

    1 MHz DPLL2 config with ZDM from 1 MHz OUT0.tcs

    I also did the 1 kHz.  I was able to align with PH_OFFSET = 1352050000.

    Note I'm AC coupled, so everything is coming out as pulses...

    1 kHz DPLL2 config with ZDM from 1 kHz OUT0.tcs

    Note the 1 kHz requires a few different items...
       - To get the low frequencies for output, you need to enable SYSREF divider and run in continuous mode.
       - For DPLL reference validation, you must use the 1 PPS detector which is good for references less than 2 kHz.
       - Depending on the jitter, you will need to increase the DPLL frequency lock detect averaging and increase the phase lock thresholds.  You can see this done in the attached config.

    73,
    Timothy

  • Dear Timothy,

    thank you for your detailed answer and the tcs-files. Both work as described and now I have to make my own experiences and will report in more detail later.

    However, scenario 2 is also important. Can you please let me know if you think that this scenario can be realized also by the LMK5C33216?

    Best regards,
    Thorsten

  • Hi Thorsten,

    Sorry, I've been OoO last week.

    For scenario 2...

    We have no input signal and the frequency (again between 1kHz and 100MHz) of the output clocks is provided by software. The both outputs should have the same frequency and an adjustable & stable phase relationship.

    Ok, sounds reasonable.  Are you able to advise me more in regard to your application?

    Do you have any maximum phase hit requirements/specs during phase adjustments?

    What resolution and range of phase adjustments do you require?  The SYSREF block also has some phase adjust ability using both digital delay and analog delay which can take effect immediately, but it will be more granular than DPLLx_PH_OFFSET.  Are you wanting to adjust the 1 kHz to anywhere in a 100 MHz period (10 ns)?

    I tried this by letting APLL3 run in free mode and feed its output divided by 4, i.e. 614.4MHz  to DPLL1 and DPLL2. To ensure that the maximum TDC1 and TDC2 frequency do not exceed 11MHz, the DPLL1 & DDPLL2 R-dividers are set to 500.

    This sounds good.  However...

    • Quick comment on functionality.  If different APLLs were programmed to produce the same output frequency, there may be a post divider cycle error in the phase.  If you were to use ZDM, you could eliminate this, but you would also need a reference.
      Normally the phase difference between APLLs wouldn't be a concern as they would be non-related frequencies anyway.
      • Do I understand correctly that you are wanting to use the two different DPLLs so you can adjust the phase very fine between related output clocks?
      • It may be possible to use the APLL3 as a reference to the DPLLs momentarily to align, but that violates the datasheet recommendation.  Further stability investigations would have to be done.
    Finally, I activated the ZDM. So far I was able to generate on OUT0 and OUT 4 two signals which are exactly at the same frequency, i.e. the phase relationship is constant (even though not exactly 0, but 5ns). But changing the DPLL1_PH_OFFSET or DPLL1_PH_OFFSET, does not result in a change of the phase relationship. The reason is probably, that I haven’t set up the ZDM correctly and that the DPPLs do not lock. I uploaded the tcs-file, maybe you can take a look at this, too.

    Sounds like you made reasonable progress here.  If you do a soft chip reset, does that result in an update to the phase properly?

    73,
    Timothy

  • Hi Timothy,

    Thanks for your reply.

    Our application is actually quite simple: we have to produce 2 output signals with the exact same frequency (that means phase stability) as a given input signal (1kHz – 100MHz) and an adjustable delay in the range of the period (1ms – 10ns).

    Meanwhile, I was successful in achieving this, by feeding OUT0 in ZDM-mode back to TDC1 and OUT4 to TDC2 (your tcs-files really helped me getting so far). After a soft-reset, the wanted phase relation-ships can be adjusted within the wanted range (1ms – 10ns).

    However, some new questions arose:

    1. To set a defined delay, I need to know how large the delay introduced by one increment of the DPLLX_PH_OFFSET register is. I have already found, that not only the VCO-frequency, but also all parameters, which can be entered in step 6 of the start page are of importance.

      Can you please provide us an algorithm for determining the delay? This is absolutely necessary for our application.

     

    1. To achieve a delay of 1ms (in case of a 1kHZ-input signal), the DPLLX_PH_OFFSET is in the range of 8e9. Interestingly, the delay increases linearly with the DPLLX_PH_OFFSET register up to a value of 7e9, corresponding to a delay of 854 µs. A further increase of the register does not lead to a greater delay and for a value of 8e9 even the phase stability is not given any more. Here, a decrease of the DPLL-LBW from 10 to 3 Hz helps, but makes the settling quite slow.

      Can you advise which are most preferable stings to be entered in step 6 to achieve phase stable delays up to 1ms?

      Can you please provide us an algorithm for determining when the phase relationship is settled? For a DPLL-LBW of 3Hz and an input signal of 1kHz the settling time is around 30sec, which is too high.

     

    1. On the output pages, there are the buttons named “INVERT”. However, if I check these, nothing happens. What do I have to do to invert the output signal? This would be very helpful, since an inverted output signal does not need to be delayed by more than 50% of the period to get a delay of a full period.

     Best regards,
    Thorsten

  • Hello Thorsten,

    Sorry for the delays... but I'll also need to get back with you in more detail later next week.

    To set a defined delay, I need to know how large the delay introduced by one increment of the DPLLX_PH_OFFSET register is. I have already found, that not only the VCO-frequency, but also all parameters, which can be entered in step 6 of the start page are of importance.

    Can you please provide us an algorithm for determining the delay? This is absolutely necessary for our application.

    Understood.

    To achieve a delay of 1ms (in case of a 1kHZ-input signal), the DPLLX_PH_OFFSET is in the range of 8e9. Interestingly, the delay increases linearly with the DPLLX_PH_OFFSET register up to a value of 7e9, corresponding to a delay of 854 µs. A further increase of the register does not lead to a greater delay and for a value of 8e9 even the phase stability is not given any more. Here, a decrease of the DPLL-LBW from 10 to 3 Hz helps, but makes the settling quite slow.

    Can you advise which are most preferable stings to be entered in step 6 to achieve phase stable delays up to 1ms?

    Can you please provide us an algorithm for determining when the phase relationship is settled? For a DPLL-LBW of 3Hz and an input signal of 1kHz the settling time is around 30sec, which is too high.

    Is it acceptable for you to issue a reset?  For example if you do a soft chip reset by pressing the button, does that help with the settling?  There are also DPLL resets on the User Control page.  Would this work for you?

    On the output pages, there are the buttons named “INVERT”. However, if I check these, nothing happens. What do I have to do to invert the output signal? This would be very helpful, since an inverted output signal does not need to be delayed by more than 50% of the period to get a delay of a full period.

    This is inverting the input which is at a high frequency (VCO post divider)... so this could not be used as you are suggesting.  However it could still be used on the SYSREF part of the divider to get a larger shift.  However when using the DPLL phase adjustments, I don't expect you will run out of room for making the phase adjustment.

    73,
    Timothy