Other Parts Discussed in Thread: LMK5C33216
we try to use the LMK5C33216EVM in Zero Delay Mode and shift the output by a defined delay using DPLLx_PH_OFFSET. In a first test scenario, I use a 10MHz clock on REF0 and generate a 10MHz output on OUT0 via APLL1.
My questions / comments are:
1. Where Do I get detailled information how to calculate and choose correct parameters for the ZDM-settings? Data sheet, EVM-Manual and Programming guide do not really help me. E.g. In section 188.8.131.52, the data sheet states that the ZDM has an influence on the VCO-calculation, but not how to handle this and if it is covered by TICS PRO.
2. How large are the minimum and the maximum achivable delay and how can I calculate it (I assume these numbers depend on the VCO frequency) ?
3. How can I access the DPLLx_PH_OFFSET registers? Only via the raw registers in the TICS PRO SW?
4. If I try to use the button 'RUN SCRIPT' in the DPLL1-window, the sofware returns a python error: 'sREF0_FREQ is not defined' (However, it is defined).
5. When will TicsPro support the ZDM feature?
6. I use a Si5338 as REF-IN. It fullfills all requirements accordiing to section 7.5, but I get a lof of RFX_MISSCLK_STATUS events. Even setting the limits to the maximum in the VALIDATION page does not improve the behaviour. On the other hand, even if I set the reference to 11MHz (instead of 10MHz) the situation does not get worse. So I had to disable the missing clock window detector. Can this cause the DPLL not to phase lock (LOPL_DPLL1 is set)?
Can you please advice?
Best Regards, Thorsten