Other Parts Discussed in Thread: ADC12DJ3200EVM,
I am currently using the ADC12DJ3200EVM which uses the LMX2582 to generate the ADC clock. I want to use PLLatinum Sim to estimate the ADC clock jitter.
I would like to sample signals from DC to 5GHz with an ENOB of 9-bits, so the RMS jitter target is tj < 1/(2*pi*Fin(max)*2^B) = 62.2fs.
PLLatinum Sim shows that the LMX2582 device can meet this jitter requirement, however, while using the tool I noticed some weird issues that I hope TI can comment on.
The following sequence of steps demonstrates an example of the issues;
1. Start PLLatinum Sim and select the LMX2582 device
2. Set Feature Level to Advanced
3. Select the "Phase Noise" tab and turn on OSC noise by selecting "Use Metrics"
4. Change the VCO frequency to 5000MHz, so that the output clock changes to 2500MHz. This is the nominal sample rate I plan to use the ADC at.
5. Change the PFD frequency to 200MHz to turn on the input doubler, and change the MASH order to 1 to clear the feedback divider warning (red background).
6. Change Kpd to 5mA.
7. Select the "Filter Designer" tab, check the "Loop Bandwidth" Auto checkbox, change the "Auto Parameter Strategy" to "Optimize Jitter", and click "Calculate Loop Filter"
The calculated jitter is 6285fs. This is a strange GUI bug, where the jitter estimate is wrong. Under the "Phase Noise" tab disable and re-enable the OSC and the jitter recalculates to 109.1fs. Disabling OSC drops the jitter to 108.9fs, so the OSC does not contribute a great deal of jitter in this configuration. Repeating steps 1 through 7, skipping step 2, and the calculated jitter is 108.8fs, and then enabling OSC increases the jitter to 109fs. This is a PLLatinum Sim bug.
My assumption for "Optimize Jitter" was that it would target minimum jitter, however, that is not the case. For Kpd = 5mA with Tj = 190fs, if I now increase Kpd, the jitter is reduced. For example, if I change Kpd without recalculating the loop filter the jitter reduces; Kpd = 9.688, Tj = 74.95fs, Kpd = 19.375mA, Tj = 58.14fs, and Kcp = 24.219mA, Tj = 55.9fs. The phase margin at these new Kpd settings is fine. If the loop filter is recalculated the jitter increases slightly.
Why does the "Optimize Jitter" strategy not sweep the loop bandwidth to find the minimum jitter?