CDCI6214: Clock Lvds output

user4078346

Other Parts Discussed in Thread: CDCI6214, CDCE6214

HI:

We have problems with some CDCI6214 in our products.We use CDCI6214RGET as the clock circuit;Enter the 16 MHZ;204.8 Mhz output;The output clock is used as the sampling clock of ADC.The circuit schematic diagram is as follows

The output clock has spurious noise as follows 171.2mhz, 237.6mhz

How can I set it to eliminate these spurious noise? Thank you!

over 4 years ago

0 Hao Z over 4 years ago

TI__Mastermind 18070 points

Hello,

Can you upload the .tcs file that you're using (In Ticspro, File -> Save).

Regards,
Hao

0 user4078346 over 4 years ago in reply to Hao Z

Prodigy 40 points

Thanks for your reply,This is our file

0 user4078346 over 4 years ago in reply to Hao Z

Prodigy 40 points

Thanks for your reply,This is our file

0 user4078346 over 4 years ago in reply to Hao Z

Prodigy 40 points

cdc_204m8.tcs

0 Hao Z over 4 years ago in reply to user4078346

TI__Mastermind 18070 points

Hello,

Please note that we've removed the FOD (fractional output divider) feature in the datasheet and issued a PCN. If you download the latest Ticspro you'll find the FODs gone.

The previous setting is not valid from the beginning, because from the attached spectrum analyzer plot, the carrier amplitude is at -20dBm which is not correct.

It is difficult to generate 204.8MHz from CDCI6214, without the FOD, because that would require the PFD frequency to go sub-MHz. I recommend you to replace the CDCI6214 with CDCE6214 which has a fractional PLL. CDCE6214 is pin compatible with CDCI6214 so no layout change is required. There's a simple frequency calculator in CDCE6214 output page where you can enter the desired output frequencies and hit the button.

Regards,
Hao

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CDCI6214: Clock Lvds output