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LMK04832: Multi clock synchronization

Kiran Kumar R
Prodigy 245 points
Part Number: LMK04832
Other Parts Discussed in Thread: LMX2820,

Hi Team,

i). we are using LMK04832  CLK synthesizer in our design for RFSoC FPGA  for multi clock synchronization. We have one Master LMK04832 driving reference signals to Clockin1 and sync/sysref to clockin0 for 4 slave LMK04832. the architecture is added below.

The master LMK04832 default has 49.152MHz input to clockin1, 122.880 MHz VCXO input to OSCin and sync/sysref signal input to sync pin of LMK. As in architecture, the Master LMK outputs device and sysref clock pair is connected to clockin1 and clockin0 of slave LMKs.  The slave LMK  required output frequencies  are as:

DCLKOUT0 : 245.76MHz( input to first LMX2820)

SDCLKOUT1: sync to first LMX2820

DCLKOUT4: 245.76MHz( input to second LMX2820)

SDCLKOUT5: sync to second LMX2820

SDCLKOUT3: 7.68MHz AMS_SYSREF

DCLKOUT6:  122.88Mhz DAC_REFCLK

SDCLKOUT7:  7.68Mhz DDR_PLY_CAP

DCLKOUT8: 122.88MHz PL_CLK

SDCLKOUT9: 7.68MHz PL_SYSREF

DCLKOUT12: 122.88Mhz ADC_REFCLK

all the 4 slave LMK output clocks need to be synchronized and aligned for Multi clock synchronization (also multi-FPGA synchronization).

How should be a Master LMK04832 device and sysref outputs need to be configured if the slave LMKs are to be used in dual loop zero delay nested mode such that the Multi clock synchronization is achieved. 

 we are using LMK first time in our designs, your values and inputs will be very helpful.

ii). To test the configurations we are using two LMK04832EVM. one EVM is used as master and Other as slave.  The setup is as : 

1. Master LMK:

a. The master LMK04832 EVM is used in dual loop zero delay nested mode with sysref feedback and sysref pulser output mode

b. The clockin1 input is set to 10.24MHz and sync is given by SPI sync through Ticspro.

c. The outputs are clockout0 : 10.24MHz , clockout2 : 20.48Mhz and sysref clock(clockout1 and clockout3) : 2.048MHz

the Master LMK04832 is operated as expected and sysref pulses are generated upon Sync SPI pulser input . The respective .tcs settings file is attached below named "Master_LMK04832EVM_settings"

Master_LMK04832EVM_settings.tcs

2. Slave LMK:

 The clockout0 and clockout1 of master LMK04832EVM  is connected to the slave LMK04832EVM clockin1 and clockin0. the slave LMK is used in re-clocked mode where the input SYSREF on clockin0 from master LMK is re-clocked and forwarded to slave LMK sysref outputs.  

Here i am not able to re-clock the sysref pulses sent from Master LMK and generate sysref outputs. The respective .tcs settings file is attached below named "Slave_LMK04832EVM_settings"

Slave_LMK04832EVM_settings.tcs

is the configurations are proper.? What changes need to be done such that the slave LMK04832EVM output sysref is obtained and synchronized. your inputs on these is very helpful.

Thanks in advance,

Kiran Kumar R

  • 0
    Prodigy 245 points

    Hi Team,

    Can you please update on this as early as possible. 

    Thanks in Advance,

    Kiran Kumar R

  • 0 in reply to Kiran Kumar R
    TI__Guru* 81750 points

    Hi Kiran,

    We will look into this and get back later, stay tuned.

  • 0 in reply to Noel Fung
    Prodigy 245 points
    Kiran Kumar R said:
    To test the configurations we are using two LMK04832EVM. one EVM is used as master and Other as slave. 

    Hi Team,

    we went further on testing the configurations using two LMK04832EVM. the set up is as:

    1. Master LMK04832 EVM

    we are using Master LMK04832 in dual loop 0-delay nested mode with SYSREF as feedback. The Sysref_Mux is set to SYSREF Continuous. as shown in above, the output pair CLOCKOUT0 and CLOCKOUT1 are used as reference and SYSREF singal to slave LMK. 

    • Output frequencies:
    • DCLOCKOUT0 - 10.24MHz
    • DCLOCKOUT2 – 10.24MHz
    • SYSREF frequency - 2.048 MHz

    the respective .Tcs file is:  Mater_LMK04832_0-delay_mode.tcs

    2. Slave LMK04832 EVM

    Slave LMK04832 is used in clock distribution mode. The Sysref_mux is set to Normal SYNC. here i understood the Clockin0 is re-clocked by Clockin1. 

    The respective .tcs file is :Slave_LMK04832_distribution_mode.tcs

    is our configurations are good (master LMK in 0-delay nested mode with sysref feedback, continuous SYSREF and slave in distribution mode )?

    can you please review our settings file and check whether the settings are proper.  If any changes required please suggest it.

    My other question is can i use master SYSREF as pulser and use these pulses as sync to slave LMKs and use slave LMK in continuous SYSREF or the above configurations are OK. Our requirement is to have continuous SYSREF at Slave LMKs outputs. 

    Thanks in advance,

    Kiran Kumar R

  • 0
    TI__Genius 12550 points

    Hi Kiran,

    Please follow the below link to get more understanding on Multi-clocks synchronization.

    https://www.ti.com/lit/an/snaa294/snaa294.pdf

    For a single LMK device (master) in Nested Zero-Delay Dual-Loop Mode (ZDM) require to satisfy few rules to provide the deterministic phase between input and output signals.

    It needs to follow both the rules of ZDM

    • Input Clock = SYSREF
    • GCD(outputs) = SYSREF, all device clocks can share an edge with the SYSREF edge 
    Kiran Kumar R said:
    Slave LMK04832 is used in clock distribution mode. The Sysref_mux is set to Normal SYNC. here i understood the Clockin0 is re-clocked by Clockin1. 

    As per your latest architecture, secondary LMK (slave) can be distribute SYSREF from CLKin0 re-clocked by CLKin1 but SYSREF divider should meet it's minimum divider value (8). currently it is 5 (10.24/2.048).

    Kiran Kumar R said:
    My other question is can i use master SYSREF as pulser and use these pulses as sync to slave LMKs and use slave LMK in continuous SYSREF or the above configurations are OK. Our requirement is to have continuous SYSREF at Slave LMKs outputs.

    Yes, you can make secondary LMK SYSREF in continuous mode by resetting the SYSREF divider from primary LMK as sync (pulse). As mentioned above, your frequencies should be adjusted so you can use minimum SYSREF divider value 8.

    Regards,

    Ajeet Pal