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TLC555: Astable operation, Output duty cycle different from simulation

Part Number: TLC555
Other Parts Discussed in Thread: CD4060B

Hi,

I would like to make, based on TLC555ID chip, an astable operation design with following output characteristics:

- Tlow = Thigh = ~3s

- Tperiod = 6s (duty cycle ~50%)

I calculate values for components, as shown below:

These calculated values are confirmed by Tina Simulation (I downloaded Astable reference design available on TI site).

The problem is that in reality I do not have the required output period (Tperiod = 3s instead of 6s, duty cycle is OK):

Yellow curve is voltage on C15 (pins 2/6).

Blue curve is output voltage (pin 3)

I understand that C15 tolerance (20%) can influence but not in a 50% ratio (R23/24 are 1% tolerance).

Does anyone have an idea what is wrong?

Thanks.

  • Pierre,

    What type of capacitor are you using? X7R COG/NPO?

  • Hi Chris,

    I'm using X5R capacitor.

    Pierre

  • Pierre,

     In most cases, the tolerance of the timing capacitor will be the largest source of timing variation. Ceramic timing capacitors should be C0G/NP0 type for the best temperature coefficient, voltage modulation, and aging characteristics. The 20% specification is nominal and doesn't include the other aforementioned variations.

    For your application the frequency is very low, less than 1Hz. 

    Quoting from our FAQ (Link below)

    "

    Minimum Frequency

     The minimum output frequency achievable is based on leakages in the timing capacitor, bias current and leakage in the timer’s ‘threshold pin’, ‘trigger pin’, ‘discharge pin’, and the PCB. The circuit board can be the biggest source of leakage if PCB condensation is possible. Leakage can also affect the accuracy of the frequency because leakage changes the effective capacitor charging and discharging currents.

    The ‘threshold pin’ and ‘trigger pin’ in the bipolar timers will start to draw a bias current near both the threshold and trigger voltages as shown in the timing window lines of figure 18. Therefore, the bias current does not affect the charging current until the end of the capacitor voltage ramp. The charging resistor current needs to be greater than the threshold pin current. The CMOS timers do not have a bias current. 

    Figure 18. Typical Bipolar ‘Threshold pin’ and ‘Trigger pin’ input bias current vs. pin voltage where Vs is 5V

     Since a large capacitance is required to achieve a very low frequency, a nano-timer can be used as an alternative for low-frequency applications. They only require a single resistor to set the time delay up to 2 hours and use little power. Another alternative is to pass the timer output to a logic multi-stage ripple counter listed in table 1 to get a final very low frequency output with a small timer capacitance value. CD4060B has its own oscillator. So the 555 timer may not be needed. "

    https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/879112/faq-how-do-i-design-a-stable-timer-oscillator-circuits-using-lmc555-tlc555-lm555-na555-ne555-sa555-or-se555

  • Hi Chris,

    Thanks for the feedback.

    As you say I plan to use an other component, more adapted for low frequency applications.

    Pierre