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LMK04826: Inquiries about setting the LMK04826

JH Shin
Guru 10870 points
Part Number: LMK04826

Hello,

My customer had intermittently an issue with JESD link error during device initialization.

The device's REFCLK and SYSREF clocks are both provided by the LMK04826.

The have found that changing the LMK04826 register 0x143 from 0x18 to 0x19 improved this error.

  1. Could you please elaborate on what is the difference between the two settings?

  2. Could you please figure out the casue of this symptom?

Thank you.

JH

  • 0
    TI__Genius 12560 points

    Hi JH,

    0x143 register setting for 0x18 or 0x19 are for assert sync from PLL2 DLD = 1 or from SYNC pin input respectively.

    Is the current first setting (0x18), SYNC_PLL2_DLD is set to 1 which will be valid for PLL2 DLD = 1 and it seems, it is not set to 1 that way SYNC is not asserting. Whereas when it is changed to (0x19), it enables the SYNC pin input and your results are improved.

    To use the SYNC feature, go to through the section 9.3.1 from the datasheet.

    Regards,

    Ajeet Pal 

  • 0 in reply to Ajeet Pal
    Guru 10870 points

    Hi Ajeet,

    My customer has some question about your comment.

    1. Does it mean that the sync event does not occur when the 0x143 register setting is 0x18?

    2. Otherwise, if it is changed to 0x19, is a sync event triggered by the SYNC pin?

    Regards,

    JH

  • 0 in reply to JH Shin
    TI__Genius 12560 points

    Hi JH,

    JH Shin said:
    1. Does it mean that the sync event does not occur when the 0x143 register setting is 0x18?

    0x18 asserting a SYNC but SYNC_Mode MUX setting (bit 0 and 1 set to 0), prevents the SYNC input and event SYNC doesn't happen.

    When you enable SYNC_MODE MUX to SYNC pin (x143 bit1,0[01]),  SYNC_PLL2_DLD (x143 bit3[1]) is asserting the sync and sync event happened.

    Regards,

    Ajeet Pal